Ignoring　some　cells　overlaps,　the　common　objective　of　very　large　scale　integration　(VLSI)　global　placement　problem　is　to　minimize　the　total　half-perimeter　wirelength　(HPWL).　Due　to　the　non-differentiability　of　HPWL,　the　differentiable　log-sum-exponential　(LSE)　wirelength　model　has　been　widely　used　to　approximate　HPWL.　In　order　to　overcome　the　disadvantage　of　fixed　parameter　value　in　LSE,　a　self-adaptive　LSE　wirelength　model　has　been　presented　in　this　paper.　In　each　iteration　of　cells　diffusion,　the　proposed　wirelength　model　is　dynamically　updated　according　to　the　overflow　of　the　circuit,　and　then　a　self-adaptive　wirelength　based　nonlinear　solver　is　used　to　solve　the　placement　problem.　Compared　with　a　state-of-the-art　LSE　based　placer,　the　experimental　results　show　that　our　wirelength　model　not　only　can　improve　the　solution　quality,　but　also　can　reduce　the　runtime.