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author:

Li, X. (Li, X..) [1] | Yu, B. (Yu, B..) [2] | Ou, J. (Ou, J..) [3] | Chen, J. (Chen, J..) [4] | Pan, D.Z. (Pan, D.Z..) [5] | Zhu, W. (Zhu, W..) [6]

Indexed by:

Scopus

Abstract:

Inserting redundant vias is necessary for improving via yield in circuit designs. Block copolymer directed self-assembly (DSA) is an emerging and promising lithography technology for the manufacture of vias and redundant vias, in which guiding templates are used to enhance the resolution. Considering manufacturability of via layer, multiple patterning (MP) lithography is also needed in advanced designs. In this paper, we study the redundant via insertion and guiding template assignment for DSA with MP problem at the postrouting stage. We propose a graph-methodology-based solution framework. First, by analyzing the structure of guiding templates, we propose a new solution expression by introducing the concept of multiplet to discard redundant solutions, and then, honoring the compact solution expression, we construct a conflict graph on the grid model. Second, we formulate the problem with single patterning (SP) as a constrained maximum weight-independent set problem, for which a fast linear interpolation algorithm is introduced to obtain a local optimal solution. To avoid undesirable local optima, we propose an effective initial solution generation method. Our framework is general and is further extended to solve the problem with double patterning (DP) or triple patterning (TP) in a two-stage manner. Experimental results validate the efficiency and effectiveness of our method. Specifically, compared with the state-of-the-art work for the problem with SP, DP, and TP, our method can save 58%, 82%, and 96% runtime, respectively. © 1993-2012 IEEE.

Keyword:

Constrained maximum-independent set; directed self-assembly (DSA); multiple patterning (MP); multiplet; redundant via insertion (RVI)

Community:

  • [ 1 ] [Li, X.]Center for Discrete Mathematics and Theoretical Computer Science, Fuzhou University, Fuzhou, 350108, China
  • [ 2 ] [Yu, B.]Department of Computer Science and Engineering, Chinese University of Hong Kong, Hong Kong, Hong Kong
  • [ 3 ] [Ou, J.]Department of Electronics and Communication Engineering, University of Texas at Austin, Austin, TX 78712, United States
  • [ 4 ] [Chen, J.]Center for Discrete Mathematics and Theoretical Computer Science, Fuzhou University, Fuzhou, 350108, China
  • [ 5 ] [Pan, D.Z.]Department of Electronics and Communication Engineering, University of Texas at Austin, Austin, TX 78712, United States
  • [ 6 ] [Zhu, W.]Center for Discrete Mathematics and Theoretical Computer Science, Fuzhou University, Fuzhou, 350108, China

Reprint 's Address:

  • [Zhu, W.]Center for Discrete Mathematics and Theoretical Computer Science, Fuzhou UniversityChina

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Source :

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

ISSN: 1063-8210

Year: 2018

Issue: 11

Volume: 26

Page: 2504-2517

1 . 9 4 6

JCR@2018

2 . 8 0 0

JCR@2023

ESI HC Threshold:170

JCR Journal Grade:2

CAS Journal Grade:3

Cited Count:

WoS CC Cited Count:

SCOPUS Cited Count: 6

ESI Highly Cited Papers on the List: 0 Unfold All

WanFang Cited Count:

Chinese Cited Count:

30 Days PV: 2

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