In　this　paper,　a　novel　low-power　synchronous　preamble　data　line　protocol　chip　design　for　serial　communication　is　proposed.　The　serial　communication　only　uses　two　wires,　chip　select　(CS)　and　secure　digital　(SD),　to　transmit　and　receive　data　between　two　devices.　The　proposed　protocol　aims　to　use　a　fewer　number　of　wires　for　the　interface,　therefore　reducing　the　complexity　as　well　as　the　area　of　the　chip　design.　Moreover,　it　increases　the　efficiency　through　a　synchronous　serial　communication-controlled　oscillator.　The　low-power　synchronous　preamble　data　line　protocol　design　was　successfully　verified　using　a　field-programmable　gate　array　(FPGA)　as　a　master　device　and　a　real　chip　as　a　slave　device.　The　signals　are　checked　through　the　use　of　a　logic　analyzer.　The　realized　low-power　synchronous　preamble　data　line　protocol　chip　design　has　a　gate　count　of　only　5.07　K　gates,　a　low　power　dissipation　of　12　mW,　and　a　chip　area　of　453,260　µm2　using　the　Taiwan　semiconductor　manufacturing　company　(TSMC)　0.18　µm　CMOS　process.　Compared　with　the　three-wire　serial　peripheral　interface　(SPI)　protocol,　the　proposed　design　has　the　advantages　of　having　a　lower　cost　and　a　lower　power　consumption.　©　2020　by　the　authors.　Licensee　MDPI,　Basel,　Switzerland.