The　complexity　of　hardware　implementation　of　the　new　generation　video　coding　standard　HEVC　has　been　greatly　improved　compared　with　the　previous　standards.　Under　the　premise　of　ensuring　coding　performance,　in　order　to　reduce　the　complexity　and　resource　consumption　of　hardware　implementation　and　improve　the　processing　speed　and　parallelism　of　hardware,　a　hardware-oriented　HEVC　intra-frame　coding　fast　algorithm　is　proposed.　The　head　bit　estimation　is　introduced　based　on　Hadamard-SATD,　which　simplifies　the　calculation　process　of　rate　distortion　cost.　The　best　mode　of　the　same　layer　neighboring　block　is　used　as　the　input　of　the　MPM,　and　the　dependence　on　the　reconstructed　data　is　removed　when　the　predicted　value　is　calculated,　and　hence　the　processing　speed　of　hardware　increases;　The　utilization　of　new　Prediction　Unit　processing　sequence　and　16-point　based　hardware　multiplexing　structure　makes　it　more　effective　to　reduce　the　usages　of　hardware　re-sources.　The　proposed　algorithm　can　reduce　the　coding　complexity　by　about　40%　without　obvious　performance　loss　compared　with　HM16.7.　Simulations　conducted　in　Xilinx　Virtex　6　show　that　the　proposed　algorithm　is　able　to　achieve　real-time　encoding　requirements　of　30　fps　1080p　and　the　required　hardware　area　can　be　reduced　by　about　45%　compared　with　the　existing　literature.　©　2019,　Beijing　China　Science　Journal　Publishing　Co.　Ltd.　All　right　reserved.