TD-SCDMA system frequency synthesizer design - Details

author：

Lin, W. (Lin, W..) ^[1] | Huang, S. (Huang, S..) ^[2] | Tong, G. (Tong, G..) ^[3]

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Abstract：

This　paper　give　a　design　of　a　TD-SCDMA　frequency　synthesizer　using　multi-ring　phase-locked　loop,　its　output　frequency　has　the　very　good　precision　and　stability.　The　specific　circuit　is　simulation　using　0.5um　BICMOS　technology　and　Cadence　Spectre　RF.　The　performance　of　whole　frequency　synthesizer　is:　its　output　frequency　range　is　2010MHz-2025MHz,　the　frequency　changing　of　stride　is200KHz,　the　frequency　locking　time　is　smaller　than　20us,　the　power　voltage　is　3.3V,　the　power　consumption　is　63.26mW.　©　2008　IEEE.

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[ 1 ] [Lin, W.]Microelectronics and Integrated Circuits of FuJian Key Laboratory, FuZhou, FuJian, China
[ 2 ] [Huang, S.]Microelectronics and Integrated Circuits of FuJian Key Laboratory, FuZhou, FuJian, China
[ 3 ] [Tong, G.]Microelectronics and Integrated Circuits of FuJian Key Laboratory, FuZhou, FuJian, China
[ 4 ] [Lin, W.]Electric Department, FuZhou University, FuJian, China

Reprint 's Address：

[Lin, W.]Microelectronics and Integrated Circuits of FuJian Key Laboratory, FuZhou, FuJian, China

Email：

mqks@fzu.edu.cn

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Source ：

International Conference on Communication Technology Proceedings, ICCT

Year： 2008

Page： 275-277

Language： English

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ESI Highly Cited Papers on the List： 0 Unfold All

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30 Days PV： 1

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