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author:

Zhang, H. (Zhang, H..) [1] | Ye, D.-Y. (Ye, D.-Y..) [2] | Guo, W.-Z. (Guo, W.-Z..) [3]

Indexed by:

Scopus

Abstract:

The obstacle-avoiding rectilinear Steiner minimal tree (OARSMT) problem is a hot topic in very-large-scale integration physical design. In practice, most of the obstacles occupy the device layer and certain lower metal layers. Therefore, we can place wires on top of the obstacles. To maximize routing resources over obstacles, we propose a heuristic for constructing a rectilinear Steiner tree with slew constraints. Our algorithm adopts an extended rectilinear full Steiner tree grid as the routing graph. We mark two types of Steiner point candidates, which are used for constructing Steiner trees and refining solutions. A shortest path heuristic variant is designed for constructing Steiner trees and it takes into account slew constraint by inhibiting growth. Furthermore, we use a pre-computed strategy to avoid calculating slew rate repeatedly. Experimental results show that our algorithm maximizes routing resources over obstacles and saves routing resources outside obstacles. Compared with the conventional OARSMT algorithm, our algorithm reduces the wire length outside obstacles by as much as 18.74% and total wire length by as much as 6.03%. Our algorithm improves the latest related algorithm by approximately 2% in terms of wire length within a reasonable running time. Additionally, calculating the slew rate only accounts for approximately 15% of the total runing time. © 2016 Elsevier B.V. All rights reserved.

Keyword:

Length-restricted; Obstacle-avoiding Rectilinear Steiner tree; Slew constraint; VLSI

Community:

  • [ 1 ] [Zhang, H.]Fujian Provincial Key Laboratory of Network Computing and Intelligent Information Processing, Fuzhou University, China
  • [ 2 ] [Zhang, H.]College of Mathematics and Computer Science, Fuzhou University, China
  • [ 3 ] [Zhang, H.]District of Universities, No. 2, Xueyuan Road, FuZhou, 350116, China
  • [ 4 ] [Ye, D.-Y.]Fujian Provincial Key Laboratory of Network Computing and Intelligent Information Processing, Fuzhou University, China
  • [ 5 ] [Ye, D.-Y.]College of Mathematics and Computer Science, Fuzhou University, China
  • [ 6 ] [Ye, D.-Y.]District of Universities, No. 2, Xueyuan Road, FuZhou, 350116, China
  • [ 7 ] [Guo, W.-Z.]Fujian Provincial Key Laboratory of Network Computing and Intelligent Information Processing, Fuzhou University, China
  • [ 8 ] [Guo, W.-Z.]College of Mathematics and Computer Science, Fuzhou University, China
  • [ 9 ] [Guo, W.-Z.]District of Universities, No. 2, Xueyuan Road, FuZhou, 350116, China

Reprint 's Address:

  • [Zhang, H.]Fujian Provincial Key Laboratory of Network Computing and Intelligent Information Processing, Fuzhou UniversityChina

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Source :

Integration, the VLSI Journal

ISSN: 0167-9260

Year: 2016

Volume: 55

Page: 162-175

1 . 0

JCR@2016

2 . 2 0 0

JCR@2023

ESI HC Threshold:175

JCR Journal Grade:4

CAS Journal Grade:4

Cited Count:

WoS CC Cited Count:

SCOPUS Cited Count: 18

ESI Highly Cited Papers on the List: 0 Unfold All

WanFang Cited Count:

Chinese Cited Count:

30 Days PV: 5

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