Ignoring　some　cell　overlaps,　global　placement　computes　the　best　position　for　each　cell　to　minimize　some　cost　metric　(e.g.,　total　wire　length,　density　overflow).　It　is　a　crucial　step　in　very　large　scale　integration　(VLSI)　physical　design,　because　it　affects　rout　ability,　performance,　and　power　consumption　of　a　circuit.　In　this　paper,　we　propose　an　Augmented　Lagrangian　method　to　solve　the　VLSI　global　placement.　In　this　method,　a　cautious　dynamic　density　weight　increasing　strategy　is　used　to　balance　the　wire　length　and　density　constraint.　We　incorporated　our　method　into　NTUplace3＇s　global　placement　framework,　and　tested　it　on　the　IBM　mixed-size　benchmark　circuits.　Experimental　results　show　that　it　obtains　high-quality　results　in　a　reasonable　running　time.　©　2012　IEEE.