Design and implementation of DVB-S2 LDPC encoder - Details

author：

Ye, Y. (Ye, Y..) ^[1] | Zhou, W. (Zhou, W..) ^[2] | Zhuang, M. (Zhuang, M..) ^[3]

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Scopus

Abstract：

In　this　paper,　a　DVB-S2　LDPC　encoder　based　on　FPGA　is　proposed　after　detailed　analysis　of　DVB-S2　LDPC　code　on　the　basis　of　irregular　repeat　accumulate　(IRA)　coding　algorithm.　This　method　not　only　uses　pipeline　technique　combined　with　all　parallel　structures　to　improve　the　coding　efficiency,　but　also　makes　use　of　VHDL　language　to　achieve　DVB-S2　encoder,　which　meets　the　requirements　of　DVB-S2　standard　on　the　condition　of　low　hardware　resources.　©　Springer-Verlag　Berlin　Heidelberg　2012.

Keyword：

DVB-S2; FPGA; Low density parity check code; VHDL hardware description language

Community：

[ 1 ] [Ye, Y.]College of Physics and Information Engineering, Fuzhou University, Fujian, Fuzhou, 350002, China
[ 2 ] [Zhou, W.]College of Physics and Information Engineering, Fuzhou University, Fujian, Fuzhou, 350002, China
[ 3 ] [Zhuang, M.]College of Physics and Information Engineering, Fuzhou University, Fujian, Fuzhou, 350002, China

Reprint 's Address：

[Ye, Y.]College of Physics and Information Engineering, Fuzhou University, Fujian, Fuzhou, 350002, China

Email：

yeyuhuang@fzu.edu.cn

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Source ：

Lecture Notes in Electrical Engineering

ISSN： 1876-1100

Year： 2012

Issue： VOL. 4

Volume： 127 LNEE

Page： 809-815

Language： English

Cited Count：

WoS CC Cited Count： 0

SCOPUS Cited Count：

ESI Highly Cited Papers on the List： 0 Unfold All

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Chinese Cited Count：

30 Days PV： 1

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