This　paper　designs　and　implements　a　dedicated　microprocessor　architecture　based　on　the　RISC-V　(the　fifth-generation　Reduced　Instruction　Set　Computing)　with　only　20　instructions　for　arbitrary-point　FFT　(Fast　Fourier　Transform)　algorithm.　Moreover,　the　corresponding　SoC　(System-on-Chip)　is　also　built　for　the　expansibility　and　reconfigurability.　The　methodology　of　software　and　hardware　co-verification　is　applied　to　validate　the　correctness　of　the　systematic　functions　by　comparing　the　simulation　results　between　MATLAB,　Visual　Studio　2019　and　VIVADO　2019.1.　Finally,　the　Xilinx　Artix-7　(XC7A100TFGG484-2)　FPGA　(Field　Programmable　Gate　Array)　platform　is　used　for　implementation　and　prototyping　of　the　proposed　hardware　system,　which　totally　uses　1897　LUTs　(Look-Up　Tables),　361　FFs　(Flip-Flops)　and　25　BRAMs　(Block　Random　Access　Memory)　and　consumes　2.016W　at　100MHz.　The　experimental　results　show　that　the　presented　system　can　realize　the　FFT　algorithm　at　any　point　by　reconfiguring　the　parameters　of　software　and　expanding　the　capacity　of　the　memory,　and　it　is　suitable　for　the　embedded　applications　due　to　the　small　area　and　low　power　consumption.　©　2021　IEEE.