Modern　circuit　layout　centerline　extraction　is　an　essential　step　in　estimating　the　parasitic　inductance　and　verifying　the　layout　performance　in　mask　verification.　As　the　continued　feature　size　shrinking　and　the　complexity　of　modern　circuit　design　keeps　growing,　heterogeneous　layout　centerline　extraction　has　become　even　more　challenging.　In　this　paper,　we　first　formulate　a　Voronoi　diagram-based　problem　transformation　to　collect　all　centerline　points.　Then,　a　graph-based　initial　centerline　generation　algorithm　is　presented　to　handle　all　invalid　centerline　points　effectively.　Finally,　a　heterogeneity-aware　centerline　optimization　method　is　proposed　to　generate　optimized　design-violation-free　centerline　results　for　irregular　structures.　Compared　with　the　state-of-the-art　commercial　3D-RC　parasitic　parameter　extraction　tool　RCExplorer　and　the　1st　place　in　the　2019　EDA　Elite　Challenge　Contest,　experimental　results　show　that　our　algorithm　achieves　the　best　average　precision　ratio　of　99.7%　on　centerline　extraction　while　satisfying　all　design　constraints.　©　2022　IEEE.