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author:

Chen, Jianli (Chen, Jianli.) [1] | Zhu, Ziran (Zhu, Ziran.) [2] | Guo, Longkun (Guo, Longkun.) [3] | Tseng, Yu-Wei (Tseng, Yu-Wei.) [4] | Chang, Yao-Wen (Chang, Yao-Wen.) [5]

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EI

Abstract:

Along with device scaling, the drain-to-drain abutment (DDA) and fence region constraints arise as emerging challenges in modern circuit designs, incurring additional difficulties, especially for designs with mixed-cell-height standard cells which have prevailed in advanced technology. This article presents the first work to address the mixed-cell-height placement problem considering the DDA and fence region constraints from post-global placement throughout the detailed placement. Our algorithm consists of three major stages: 1) preprocessing; 2) legalization; and 3) detailed placement. At the preprocessing stage, we align cells to the desired rows that meet the region constraint, considering the total cell displacement and the distribution ratio of source nodes to drain nodes simultaneously. After deciding the cell ordering of every row, we first propose an interval concept to handle fixed macros and fence regions and then apply the robust modulus-based matrix splitting iteration method to remove all cell overlaps with minimized total displacement at the legalization stage. For detailed placement, unlike the existing works that can handle the DDA constraint only for single rows, we propose a satisfiability-based approach that considers the whole layout to fix the DDA violations more effectively. Besides, we further present an integer linear program (ILP)-based method to optimize the cell displacement without increasing the DDA violations. Compared with a shortest-path method, experimental results show that our proposed algorithm can significantly reduce cell violations, average cell displacement, and maximum cell displacement, in a comparable runtime. © 1982-2012 IEEE.

Keyword:

Abutments (bridge) Authentication Cells Contracts Cytology Fences Integer programming Iterative methods

Community:

  • [ 1 ] [Chen, Jianli]State Key Laboratory of Asic and System, Fudan University, Shanghai; 200433, China
  • [ 2 ] [Zhu, Ziran]National Asic System Engineering Center, School of Electronic Science and Engineering, Southeast University, Nanjing; 210096, China
  • [ 3 ] [Guo, Longkun]College of Mathematics and Computer Science, Fuzhou University, Fuzhou; 350116, China
  • [ 4 ] [Tseng, Yu-Wei]Graduate Institute of Electronics Engineering, National Taiwan University, Taipei; 106, Taiwan
  • [ 5 ] [Chang, Yao-Wen]Department of Electrical Engineering, Graduate Institute of Electronics Engineering, National Taiwan University, Taipei; 106, Taiwan

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Source :

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

ISSN: 0278-0070

Year: 2022

Issue: 4

Volume: 41

Page: 1103-1115

2 . 9

JCR@2022

2 . 7 0 0

JCR@2023

ESI HC Threshold:66

JCR Journal Grade:2

CAS Journal Grade:3

Cited Count:

WoS CC Cited Count: 0

SCOPUS Cited Count: 3

ESI Highly Cited Papers on the List: 0 Unfold All

WanFang Cited Count:

Chinese Cited Count:

30 Days PV: 3

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