Timing　optimization　has　always　been　a　key　issue　affecting　the　chip　performance.　Most　of　the　previous　layer　assignment　algorithms　mainly　optimize　timing　from　the　perspective　of　interconnect　delay,　and　often　ignore　the　impact　of　slew　on　signal　integrity.　Therefore,　this　paper　proposes　LA-SVR,　a　high-performance　layer　assignment　algorithm　with　slew　violations　reduction.　The　proposed　algorithm　mainly　includes　three　key　techniques:　1)　an　effective　classified　reassignment　strategy　is　proposed　to　re-assign　nets　in　terms　of　different　optimization　priorities　for　overflow　avoidance;　2)　an　effective　net　adjustment　method　is　adopted　to　reduce　the　potential　slew　violations;　3)　a　layer　restricting　strategy　is　proposed　to　optimize　delay　of　nets　and　slew　violations　simultaneously　by　restricting　the　candidate　better　routing　layers　of　different　nets.　Experimental　results　show　that　the　proposed　algorithm　has　a　significant　effect　on　slew　violations　reduction.　©　2022　IEEE.