Timing　optimization　plays　an　essential　role　in　very　large　scale　integration　(VLSI)　design　closure.　Traditional　placement　algorithms　seldom　consider　the　complex　timing　constraints　and　thus　may　lead　to　inferior　timing　results.　In　this　paper,　we　propose　a　timing-aware　virtual　path　optimization　strategy　for　VLSI　global　placement.　The　proposed　algorithm　uses　a　novel　virtual　net　method　and　simultaneously　optimizes　the　timing　and　wirelength.　We　evaluate　our　results　on　the　ICCAD　2015　contest　benchmarks　and　industrial　benchmarks.　Compared　with　the　widely　used　net-weighting　method,　experimental　results　show　that　our　algorithm　achieves　not　only　a　11.2%　improvement　in　worst　negative　slack　but　also　a　15.9%　in　total　negative　slack.　©　2022　IEEE.