Approximate　computing　is　an　emerging　and　effective　method　for　reducing　energy　consumption　in　digital　circuits,　which　is　critical　for　energy-efficient　performance　improvement　of　edge-computing　devices.　In　this　paper,　we　propose　a　low-power　DNN　accelerator　with　novel　signed　approximate　multiplier　based　on　probability-optimized　compressor　and　error　compensation.　The　probability-optimized　compressor　is　customized　for　partial　product　matrix　(PPM)　of　signed　operands,　which　gets　the　optimal　logic　circuit　after　probabilistic　analysis　and　optimization.　At　the　same　time,　we　explored　the　PPM　truncation　method,　found　out　the　impact　of　different　partial　product　(PP)　truncation　numbers　on　circuit　benefit　and　error,　and　achieved　a　more　ideal　performance-error　tradeoff　through　a　reasonable　error　compensation　method.　In　the　optimal　case　of　8　bits,　the　proposed　approximate　multiplier　saves　49.84%　power,　46.41%　area　and　24.65%　delay　compared　to　the　exact　multiplier.　We　employed　the　proposed　approximate　multiplier　in　the　vector　systolic　array　as　the　processing　element　(PE).　Under　the　VGG-16　evaluation,　the　proposed　accelerator　achieves　performance　improvement　of　energy　efficiency　1.96×　,　while　the　error　loss　was　only　0.95%.　©　2020　IEEE.