Placement　is　a　critical　stage　for　VLSI　timing　closure.　A　global　placer　without　considering　timing　delay　might　lead　to　inferior　solutions　with　timing　violations.　This　paper　proposes　an　electrostatics-based　timing　optimization　method　for　VLSI　global　placement.　Simulating　the　optimal　buffering　behavior,　we　first　present　an　analytical　delay　model　to　calculate　each　connection　delay　accurately.　Then,　a　timing-driven　block　distribution　scheme　is　developed　to　optimize　the　critical　path　delay　while　considering　the　path-sharing　effect.　Finally,　we　develop　a　timing-aware　precondition　technique　to　speed　up　placement　convergence　without　degrading　timing　quality.　Experimental　results　on　industrial　benchmark　suites　show　that　our　timing-driven　placement　algorithm　outperforms　a　leading　commercial　tool　by　6.7%　worst　negative　slack　(WNS)　and　21.6%　total　negative　slack　(TNS).　©　2024　EDAA.