Placement　is　a　critical　stage　for　VLSI　routability　optimization.　A　placement　engine　without　considering　the　layout　congestion　might　lead　to　poor　solutions　with　routing　failures.　This　paper　introduces　a　Coulomb　force-based　global　placement　framework　that　addresses　global　and　local　routing　congestions.　We　first　present　a　routing　path-based　cell　padding　strategy　for　local　congestion　mitigation.　Then,　we　construct　a　routability-aware　placement　model　that　utilizes　virtual　Coulomb　forces　to　eliminate　crucial　global　congestion.　Compared　with　a　leading　academic　placer,　RePlAce,　and　the　advanced　commercial　tool,　Innovus,　the　experimental　results　on　industrial　benchmark　suites　show　that　our　proposed　algorithm　achieves　the　best　routability　within　the　shortest　runtime.　©　2024　Copyright　is　held　by　the　owner/author(s).　Publication　rights　licensed　to　ACM.