Timing-driven　routing　is　crucial　in　complex　circuit　design.　Existing　shallow-light　Steiner　tree　construction　methods　balance　between　wire　length　(WL)　and　source-sink　path　length　(PL)　but　lack　in　delay.　Conversely,　previous　delay-driven　methods　prioritize　delay　but　result　in　longer　WL　and　PL,　making　them　suboptimal.　In　this　article,　we　show　that　simultaneously　reducing　the　WL　and　PL　can　effectively　reduce　the　delay.　Furthermore,　we　investigate　how　delay　changes　during　the　reduction　of　PL.　Guided　by　the　theoretical　findings,　we　develop　a　rectilinear　shallow-light　Steiner　tree　construction　algorithm　designed　to　reduce　delay　meanwhile　maintaining　a　bounded　WL.　Furthermore,　a　delay-driven　edge　shifting　algorithm　is　proposed　to　fine　tune　the　tree’s　topology,　further　reducing　delay.　We　show　that　our　proposed　edge　shifting　algorithm　can　return　a　local　Pareto　optimal　solution　when　repeatedly　applied.　Experimental　results　show　that　our　algorithm　achieves　the　lowest　total　delay　compared　to　previous　methods　while　maintaining　competitive　WL.　Moreover,　for　nets　with　pins　that　have　timing　information,　our　algorithm　can　generate　the　most　suitable　Steiner　Tree　based　on　the　timing　information.　In　addition,　extended　experiments　highlight　the　positive　impact　of　constructing　rectilinear　Steiner　trees　with　minimized　total　delay.　©　1982-2012　IEEE.