Multi-bit　flip-flops　(MBFFs)　are　widely　employed　in　modern　digital　design　due　to　their　reduced　power　and　area　consumption　compared　to　single-bit　flip-flops　(SBFFs).　In　this　paper,　we　present　an　MBFF-based　framework　that　simultaneously　optimizes　the　crucial　power,　area,　and　timing　metrics.　First,　we　present　a　mean　shift-based　clustering　algorithm　to　generate　power　and　area-friendly　clusters　while　considering　multiple　clocks.　Then,　a　feasible-region-based　declustering　method　is　developed　to　produce　the　desired　timing　solution.　Finally,　we　propose　a　timing-aware　refinement　strategy　to　further　improve　the　solution　quality.　Compared　with　the　competitive　works,　the　experimental　results　show　that　our　proposed　algorithm　achieves　the　best　performance　within　the　shortest　runtime.　©　2025　IEEE.