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学者姓名：王仁平
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Abstract ：
The Internet of Things (IoT) is a crucial component of the contemporary information industry and represents a significant advancement in information technology aimed at enhancing both human productivity and daily existence. Their applications are extensive and far-reaching. However, the present state of research on the design of low-cost IoT SoC chips leveraging open-source instruction set architectures lacks the requisite depth and breadth. To meet the requirements of low-cost IoT system-on-chip (SoC) development, this study presents a commodity code recognition SoC chip based on the RISC-V instruction set architecture, which is capable of performing image acquisition and barcode recognition. The proposed system comprises two main components: a low-power RISC-V processor and an image recognition module. This study initially enhanced the speed, accuracy, and area efficiency of the hardware design of a commodity barcode image-recognition module. Subsequently, the image recognition control module was developed using the RISC-V processor and CMOS image sensor OV7670, and the outcomes of image recognition were accessed through interrupts. The processing speed for collecting and identifying $640\times 480$ images on the FPGA board was 11.4FPS, and the image recognition rate was 99.5%. The chip was taped-out using the UMC55n process, which successfully decoded the barcodes and output the results at a working frequency of 40 MHz.
Keyword ：
Barcode Barcode MPW MPW RISC-V RISC-V SoC chip SoC chip
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| GB/T 7714 | Lin, Sijie , Wang, Renping , Cai, Ting et al. A Custom RISC-V Based SOC Chip for Commodity Barcode Identification [J]. | IEEE ACCESS , 2024 , 12 : 61708-61716 . |
| MLA | Lin, Sijie et al. "A Custom RISC-V Based SOC Chip for Commodity Barcode Identification" . | IEEE ACCESS 12 (2024) : 61708-61716 . |
| APA | Lin, Sijie , Wang, Renping , Cai, Ting , Zeng, Yunze . A Custom RISC-V Based SOC Chip for Commodity Barcode Identification . | IEEE ACCESS , 2024 , 12 , 61708-61716 . |
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Graph convolution networks (GCN) have demonstrated success in learning graph structures; however, they are limited in inductive tasks. Graph attention networks (GAT) were proposed to address the limitations of GCN and have shown high performance in graph -based tasks. Despite this success, GAT faces challenges in hardware acceleration, including: 1) The GAT algorithm has difficulty adapting to hardware; 2) challenges in efficiently implementing Sparse matrix multiplication (SPMM); and 3) complex addressing and pipeline stall issues due to irregular memory accesses. To this end, this paper proposed SH-GAT, an FPGA-based GAT accelerator that achieves more efficient GAT inference. The proposed approach employed several optimizations to enhance GAT performance. First, this work optimized the GAT algorithm using split weights and softmax approximation to make it more hardware -friendly. Second, a load -balanced SPMM kernel was designed to fully leverage potential parallelism and improve data throughput. Lastly, data preprocessing was performed by pre -fetching the source node and its neighbor nodes, effectively addressing pipeline stall and complexly addressing issues arising from irregular memory access. SH-GAT was evaluated on the Xilinx FPGA Alveo U280 accelerator card with three popular datasets. Compared to existing CPU, GPU, and state-of-the-art (SOTA) FPGA-based accelerators, SH-GAT can achieve speedup by up to 3283x, 13x, and 2.3x.
Keyword ：
accelerator accelerator co-design co-design FPGA FPGA graph graph graph attention networks graph attention networks
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| GB/T 7714 | Wang, Renping , Li, Shun , Tang, Enhao et al. SH-GAT: Software-hardware co-design for accelerating graph attention networks on FPGA [J]. | ELECTRONIC RESEARCH ARCHIVE , 2024 , 32 (4) : 2310-2322 . |
| MLA | Wang, Renping et al. "SH-GAT: Software-hardware co-design for accelerating graph attention networks on FPGA" . | ELECTRONIC RESEARCH ARCHIVE 32 . 4 (2024) : 2310-2322 . |
| APA | Wang, Renping , Li, Shun , Tang, Enhao , Lan, Sen , Liu, Yajing , Yang, Jing et al. SH-GAT: Software-hardware co-design for accelerating graph attention networks on FPGA . | ELECTRONIC RESEARCH ARCHIVE , 2024 , 32 (4) , 2310-2322 . |
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在集成电路的实际运用中,由于电压的不稳定和芯片电流密度的提升,容易导致电压降过大,从而影响芯片的性能和可靠性.为了提高集成电路的性能和可靠性,需要对电路中的电压降进行分析和优化.本文基于中芯国际55nm工艺完成了一款条形码模块的物理实现,结合业界主流EDA工具的自动化修复流程对其电压降进行分析和优化,在静态电压降和动态电压降分析过程中电压降分别降低了21.37％和27.79％,最终达到签核要求.与传统手动修复电压降的方法相比,该方法可以有效减小修复电压降过程中对绕线资源的占用,达到提高芯片有效利用率的目的.
Keyword ：
功耗优化技术 功耗优化技术 动态电压降 动态电压降 电压降分析 电压降分析 静态电压降 静态电压降
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| GB/T 7714 | 雷传煌 , 王仁平 , 卢朝辉 . 条形码模块的电压降分析与优化 [J]. | 电子制作 , 2024 , 32 (3) : 55-58,35 . |
| MLA | 雷传煌 et al. "条形码模块的电压降分析与优化" . | 电子制作 32 . 3 (2024) : 55-58,35 . |
| APA | 雷传煌 , 王仁平 , 卢朝辉 . 条形码模块的电压降分析与优化 . | 电子制作 , 2024 , 32 (3) , 55-58,35 . |
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工程变更指令(Engineering Change Order,ECO)在芯片设计当中是一种非常有效地解决芯片功能或时序问题的方法.本文以自研的条形码识别芯片为例,提出一种结合逻辑验证的从寄存器传输级(Register Transfer Level,RTL)电路到GDSII版图的自动化ECO流程.介绍了基于综合工具、逻辑验证工具,布局布线工具的自动化ECO流程应用.同时围绕Conformal工具进行逻辑等效验证及ECO补丁生成,能够更直观地了解设计的变更点.且所有操作均可由自动化脚本完成,相较于传统的ECO流程,自动化程度更高,通过调用的综合工具使电路能更好地满足时序约束,大大降低了时间和人力成本,加快了芯片生产周期.
Keyword ：
ECO ECO 工程变更 工程变更 芯片设计 芯片设计 逻辑验证 逻辑验证
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| GB/T 7714 | 曾云泽 , 林思杰 , 卢朝辉 et al. 条形码识别SoC芯片实现自动化ECO [J]. | 电子制作 , 2024 , 32 (18) : 25-28 . |
| MLA | 曾云泽 et al. "条形码识别SoC芯片实现自动化ECO" . | 电子制作 32 . 18 (2024) : 25-28 . |
| APA | 曾云泽 , 林思杰 , 卢朝辉 , 王仁平 . 条形码识别SoC芯片实现自动化ECO . | 电子制作 , 2024 , 32 (18) , 25-28 . |
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以车牌识别专用芯片设计为前提,应用图像处理的方式设计和优化多色车牌识别系统.在车牌定位算法中将数学形态学定位与颜色定位相结合,弥补了传统单一定位算法定位不准确的缺陷;在车牌二值化过程中采用去背景二值化算法,减弱了光照不均匀等因素对车牌二值化的影响;在字符分割算法中对投影法进行优化,对字符进行粗分割后,对可能受到影响的字符进行细分割,提高了字符分割的准确性;在字符识别算法中采取二次匹配等操作对传统的模板匹配法进行优化,进一步提高了车牌识别率.仿真结果表明,该系统对不同颜色车牌号综合识别率达到了94.5%,为后续芯片设计提供算法依据.
Keyword ：
字符分割 字符分割 字符识别 字符识别 车牌定位 车牌定位 车牌识别 车牌识别
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| GB/T 7714 | 卢朝辉 , 王仁平 , 蔡挺 . 基于Matlab的多色车牌识别系统优化设计 [J]. | 电子设计工程 , 2024 , 32 (21) : 137-140 . |
| MLA | 卢朝辉 et al. "基于Matlab的多色车牌识别系统优化设计" . | 电子设计工程 32 . 21 (2024) : 137-140 . |
| APA | 卢朝辉 , 王仁平 , 蔡挺 . 基于Matlab的多色车牌识别系统优化设计 . | 电子设计工程 , 2024 , 32 (21) , 137-140 . |
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基于 180 nm CMOS工艺,设计了一种应用于物联网的 14-bit 逐次逼近型模数转换器(Successive Approximation Analog-to-Digital Converter,SAR ADC).电容阵列采用分段和冗余技术,高段电容加入了两位冗余电容,在提高ADC的精度与线性度的同时也减少了版图面积.为了实现高精度,采用了一种基于电荷泵的失调电压降低技术的动态比较器,基于电荷泵的逐次逼近比较环路改变全动态预放大器两个输入晶体管的衬底电压差值,有效的补偿了失调电压,最终稳定在一个小的失调步长内.相比于传统静态预放大器,全动态预放大器节省了更多的功耗,相比于现有电荷泵补偿技术,使用更加简单的校准逻辑,大大减少数字电路的开销.动态器件匹配(DEM)技术用于提高电容阵列最高 3 位的电容的匹配度,将最高 3 位的电容拆分为大小相等的 7 个电容,让电容转换过程中,被选中的概率相同,将电容失配的误差平均化,从而将谐波平均分布到频域范围,以减少电容失配的影响.仿真结果表明,在采样频率为 4 kS/s时,供电电压为 1.8 V的条件下,无杂散动态范围为 94.9 dB,功耗为1.002 μW,有效位数为 13.01 bit.
Keyword ：
低功耗 低功耗 分段电容阵列 分段电容阵列 物联网 物联网 逐次逼近型模数转换器 逐次逼近型模数转换器 高精度比较器 高精度比较器
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| GB/T 7714 | 翁烜非 , 魏聪 , 周圻坤 et al. 一种应用于物联网的高精度SAR ADC [J]. | 微电子学与计算机 , 2024 , 41 (11) : 60-67 . |
| MLA | 翁烜非 et al. "一种应用于物联网的高精度SAR ADC" . | 微电子学与计算机 41 . 11 (2024) : 60-67 . |
| APA | 翁烜非 , 魏聪 , 周圻坤 , 王仁平 , 魏榕山 . 一种应用于物联网的高精度SAR ADC . | 微电子学与计算机 , 2024 , 41 (11) , 60-67 . |
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目的 加快中医望诊装置在社区家庭等场景中的应用普及.方法 开展了复杂背景下便携式标准化高清面舌图像采集装置研究.完成了装置的硬件设计,其尺寸为20 ×22 ×23cm3,达到了便携性要求.基于现有Mediapipe人脸特征检测算法和飞行时间(ToF)测距算法,提出了一种智能感知算法以获取使用者脸部区域的纵深、水平、垂直等3维度的位置信息;提出一种实时摄像头位移测速算法以实现其快速升降;将查找表与爬坡算法相结合,实现了一种摄像头快速自动变焦对焦算法;基于Haar级联分类器完成了一款轻量级舌体检测模型的设计;实验结果显示,在同等硬件资源下本文舌体检测模型准确率和漏检率基本与YOLOv5算法相当,但其速度提升了约23倍.结果 通过装置的语音引导和摄像头位置自适应调整,30位未经培训人员能够快速完成位姿纠正及面舌像的标准化图像采集,平均采集时间为33秒.结论 为中医望诊面舌图像采集装置的推广提供了一种新思路.
Keyword ：
Haar级联分类器 Haar级联分类器 中医面舌诊 中医面舌诊 位姿纠正 位姿纠正 图像识别 图像识别
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| GB/T 7714 | 胡真骁 , 杨朝阳 , 吴长汶 et al. 便携式复杂背景下标准化高清面舌图像采集装置研究 [J]. | 时珍国医国药 , 2024 , 35 (15) : 3493-3497 . |
| MLA | 胡真骁 et al. "便携式复杂背景下标准化高清面舌图像采集装置研究" . | 时珍国医国药 35 . 15 (2024) : 3493-3497 . |
| APA | 胡真骁 , 杨朝阳 , 吴长汶 , 伍明诚 , 王仁平 , 阴亚东 . 便携式复杂背景下标准化高清面舌图像采集装置研究 . | 时珍国医国药 , 2024 , 35 (15) , 3493-3497 . |
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This paper introduces a discrete-time delta-sigma ADC for the Internet of Things (IoT) applications. It utilizes second-order 4-bit successive approximation register (SAR) quantizer architecture based on the oversampling technique to ensure a sufficiently high SQNR. Additionally, dynamic weighted averaging (DWA) technique is employed to achieve good feedback CDAC linearity. System-level analysis and circuit implementation analysis are introduced in detail. The implemented prototype of this architecture is manufactured using a 180 nm CMOS process. The proposed ADC, operating at a supply voltage of 1.8 V and a sampling frequency of 2.5 MHz, including biasing circuitry, consumes a total power of 1.3 mW. This ADC achieves a DR of 102.6 dB, SNR of 101.5 dB, and SNDR of 98.6 dB within a 10 kHz bandwidth. As a result, the Schreier figure-of-merits (FoM) for SNR, SNDR and DR is 167.46 dB, 170.36 dB, and 171.46 dB.
Keyword ：
Delta -sigma Delta -sigma Discrete -time Discrete -time Internet of Things (IoT) Internet of Things (IoT) SAR quantizer SAR quantizer
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| GB/T 7714 | Wei, Cong , Chen, Chengying , Huang, Gongxing et al. A 1.8 V 98.6 dB SNDR discrete-time CMOS delta-sigma ADC [J]. | MICROELECTRONICS JOURNAL , 2023 , 144 . |
| MLA | Wei, Cong et al. "A 1.8 V 98.6 dB SNDR discrete-time CMOS delta-sigma ADC" . | MICROELECTRONICS JOURNAL 144 (2023) . |
| APA | Wei, Cong , Chen, Chengying , Huang, Gongxing , Huang, Lijie , Wang, Renping , Wei, Rongshan . A 1.8 V 98.6 dB SNDR discrete-time CMOS delta-sigma ADC . | MICROELECTRONICS JOURNAL , 2023 , 144 . |
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This paper presents a low-power capacitive-to-digital converter (CDC) based on incremental delta-sigma modulator. It utilizes a zoom-in sensing capacitor that is insensitive to parasitic capacitance, improving the capacitance resolution. The use of a high-gain, PVT-robust current-starved OTA and a dynamic bias comparator enhances the efficiency of the system. An ultra-low-power bias circuit is integrated into the system, further improving integration and efficiency. The proposed CDC is fabricated using a 180 nm CMOS process. Operating at a 1.2 V supply voltage and a 250 kHz sampling frequency. With a measurement time of 0.8 ms, the capacitance resolution is 107.6 aF, and the power consumption is 10.27 mu W. The figure-of-merits (FoM) is 2.06 pJ/step.
Keyword ：
Capacitive-to-digital Capacitive-to-digital Current-starved OTA Current-starved OTA Delta-sigma Delta-sigma Low power Low power
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| GB/T 7714 | Wei, Rongshan , Wei, Cong , Huang, Lijie et al. Low power capacitive-to-digital converter based on incremental delta-sigma modulator [J]. | MICROELECTRONICS JOURNAL , 2023 , 142 . |
| MLA | Wei, Rongshan et al. "Low power capacitive-to-digital converter based on incremental delta-sigma modulator" . | MICROELECTRONICS JOURNAL 142 (2023) . |
| APA | Wei, Rongshan , Wei, Cong , Huang, Lijie , Huang, Gongxing , Wang, Renping , Hu, Wei . Low power capacitive-to-digital converter based on incremental delta-sigma modulator . | MICROELECTRONICS JOURNAL , 2023 , 142 . |
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A voltage reference is indispensable in Integrated Circuits. To improve the limited linear output voltage range and energy efficiency of a voltage reference, we innovatively propose a switched-capacitor-based programmable voltage reference scheme employing inverter-based OTAs to reduce the power consumption, simultaneously using a novel Correlated Level Shifting (CLS) technique (without active overhead) to enhance the OTA's DC gain and integral gain. Experimented with SMIC 180 nm CMOS technology, a scheme-based voltage reference realizes a programable output voltage range from 266 to 995 mV at -30 to 120 degrees C, and the corresponding temperature coefficient (TC) ranges from 82.4 to 99.5 ppm/degrees C. The power consumption is 976 nW. Furthermore, comparative experiments and evaluations with other schemes have unequivocally verified the superiority of our proposed scheme, characterized by its high energy efficiency and wide output voltage range. The scheme can be suitably deployed in a multitude of novel edge-data processing systems.
Keyword ：
correlated level shifting correlated level shifting switched-capacitor switched-capacitor voltage reference voltage reference
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| GB/T 7714 | Wei, Rongshan , Chen, Chu , Wei, Cong et al. An Energy-Efficient Inverter-Based Voltage Reference Scheme with Wide Output Range Using Correlated Level Shifting Technique [J]. | ELECTRONICS , 2023 , 12 (24) . |
| MLA | Wei, Rongshan et al. "An Energy-Efficient Inverter-Based Voltage Reference Scheme with Wide Output Range Using Correlated Level Shifting Technique" . | ELECTRONICS 12 . 24 (2023) . |
| APA | Wei, Rongshan , Chen, Chu , Wei, Cong , Wang, Renping , Huang, Lijie , Zhou, Qikun et al. An Energy-Efficient Inverter-Based Voltage Reference Scheme with Wide Output Range Using Correlated Level Shifting Technique . | ELECTRONICS , 2023 , 12 (24) . |
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