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学者姓名：魏榕山
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The Ordered Escape Routing (OER) problem, which is an NP-hard problem, is critical to PCB design. Primary methods based on integer linear programming (ILP) work well on small-scale PCBs with fewer pins. However, when dealing with large-scale instances, traditional ILP strategies frequently cause time violations as the number of variables increases due to time-consuming preprocessing. In addition, heuristic algorithms have a time advantage when dealing with specific problems. In this paper, We propose an efficient two-stage escape routing method that employs LP for global routing and uses a heuristic algorithm to deal with the path intersection problem to minimize wiring length and runtime for large-scale PCBs. We first model the OER problem as a min-cost multi-commodity flow problem and use ILP to solve it. Then, we relax the non-crossing constraints and transform the ILP model into an LP model to reduce the runtime. we also construct a crossing graph according to the intersection of routing paths and propose a heuristic algorithm to locate congestion quickly. Finally, we reduce the local area capacity and allow global automatic congestion optimization. Compared with the state-of-the-art work, experimental results show that our method can reduce the routing time by 60% and handle larger-scale PCB escape routing problems.
Keyword ：
Heuristic algorithm Heuristic algorithm Linear programming Linear programming Min-cost multi-commodity flow Min-cost multi-commodity flow Ordered escape routing Ordered escape routing
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| GB/T 7714 | Lin, Disi , Chen, Chuandong , Wei, Rongshan et al. Two stage Ordered Escape Routing combined with LP and heuristic algorithm for large scaled PCB [J]. | INTEGRATION-THE VLSI JOURNAL , 2025 , 100 . |
| MLA | Lin, Disi et al. "Two stage Ordered Escape Routing combined with LP and heuristic algorithm for large scaled PCB" . | INTEGRATION-THE VLSI JOURNAL 100 (2025) . |
| APA | Lin, Disi , Chen, Chuandong , Wei, Rongshan , Liu, Qinghai , He, Huan , Zhu, Ziran et al. Two stage Ordered Escape Routing combined with LP and heuristic algorithm for large scaled PCB . | INTEGRATION-THE VLSI JOURNAL , 2025 , 100 . |
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For high-precision sensor applications, high dynamic range discrete-time delta-sigma modulators (DSMs) are key components. For the design of high dynamic range DSMs, the system architecture is crucial. The system requires strong in-band noise suppression for small input amplitudes and a large maximum stable amplitude (MSA) for large input amplitudes. This article presents the system design and optimization method of discrete- time delta-sigma modulator. It provides a detailed discussion on the behavior-level modeling and characteristics of low-bit and multi-bit quantizers. Additionally, design considerations of quantizers in DSM systems are analyzed. An approach for optimizing DSM systems by leveraging the properties of quantizers is proposed, along with a simple optimization case study. Potential future application scenarios are also presented. The purpose of this article is to offer design guidelines for developing well-performing DSMs systems.
Keyword ：
Delta-sigma modulator (DSM) Delta-sigma modulator (DSM) Discrete-time Discrete-time Dynamic range Dynamic range Quantizer Quantizer
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| GB/T 7714 | Peng, Ziqiang , Wei, Cong , Huang, Lijie et al. Design and optimization of discrete-time delta-sigma modulators [J]. | MICROELECTRONICS JOURNAL , 2025 , 156 . |
| MLA | Peng, Ziqiang et al. "Design and optimization of discrete-time delta-sigma modulators" . | MICROELECTRONICS JOURNAL 156 (2025) . |
| APA | Peng, Ziqiang , Wei, Cong , Huang, Lijie , Lai, Jinze , Lu, Xiaoqiang , Wei, Rongshan . Design and optimization of discrete-time delta-sigma modulators . | MICROELECTRONICS JOURNAL , 2025 , 156 . |
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This paper describes the analysis and design of a discrete-time (DT) fully dynamic 3-0 multi-stage noise-shaping (MASH) delta-sigma (Delta Sigma) analog-to-digital converter (ADC). Through system-level analysis, error source analysis, nonlinearity analysis and modeling of the integrators, and detailed considerations for circuit implementation, the trade-offs between design parameters in the 3-0 MASH Delta Sigma ADC were evaluated. The proposed ADC is fabricated and measured in a 180 nm CMOS process, achieving a DR, peak SNDR, and SFDR of 100.2 dB, 98.5 dB, and 116.7 dB, respectively, within a 2.56 kHz bandwidth, consuming only 20.1 mu W. As a result, the Schreier figure-of-merit (FoM) for SNDR and DR are 179.6 dB and 181.3 dB, respectively. The measurement results of the prototype 3-0 MASH Delta Sigma ADC closely matched the theoretical predictions. This consistency between the measurements and the theoretical analysis confirms the reliability of the design approach in achieving the expected performance.
Keyword ：
Active filters Active filters analog-to-digital converter (ADC) analog-to-digital converter (ADC) Circuits Circuits delta-sigma (Delta Sigma) delta-sigma (Delta Sigma) Digital filters Digital filters discrete-time (DT) discrete-time (DT) Energy efficiency Energy efficiency Gain Gain Multi-stage noise shaping Multi-stage noise shaping Multi-stage noise-shaping (MASH) Multi-stage noise-shaping (MASH) Noise Noise Power demand Power demand Quantization (signal) Quantization (signal) Transfer functions Transfer functions
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| GB/T 7714 | Wei, Cong , Huang, Lijie , Wei, Rongshan et al. Analysis and Design of a Discrete-Time 3-0 MASH Delta-Sigma ADC With 100.2 dB Dynamic Range [J]. | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS , 2025 . |
| MLA | Wei, Cong et al. "Analysis and Design of a Discrete-Time 3-0 MASH Delta-Sigma ADC With 100.2 dB Dynamic Range" . | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS (2025) . |
| APA | Wei, Cong , Huang, Lijie , Wei, Rongshan , Lu, Xiaoqiang , Tan, Zhichao . Analysis and Design of a Discrete-Time 3-0 MASH Delta-Sigma ADC With 100.2 dB Dynamic Range . | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS , 2025 . |
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The high frequency characteristics of rapid single-flux-quantum (RSFQ) circuits poses a great challenge to circuit layout design. In order to solve the circuit delay problem caused by the high frequency characteristics of RSFQ, delay elements such as passive transmission line can be used in the routing stage. The delay of a passive transmission line is roughly proportional to its length, and the power consumption of the passive transmission line does not increase with the increase of the wirelength, so length matching routing is a crucial problem for RSFQ circuits. Therefore, we propose an efficient RSFQ circuit routing algorithm considering length matching, including the following key strategies: 1) when generating the initial path, a method of detour routing is presented to meet the partial length matching of passive transmission lines without changing the initial routing space; 2) an iterative resource insertion algorithm based on region-awareness is utilized to reduce the area of additional resources needed to be added; 3) a length-matching driven routing algorithm considering blocking cost is designed, which improves the resource utilization of routing space. Experimental results show that, compared with existing multi-terminal routing algorithms, the proposed algorithm reduces the area required for routing by 8% and the running time by 36%, thus achieving fast and high-quality routing results. © 2025 Science Press. All rights reserved.
Keyword ：
Electric delay lines Electric delay lines Routing algorithms Routing algorithms Routing protocols Routing protocols
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| GB/T 7714 | Liu, Genggeng , Yu, Yantao , Zhou, Ruping et al. Rapid Single-Flux-Quantum Circuit Routing Algorithm Considering Length Matching [J]. | Computer Research and Development , 2025 , 62 (5) : 1151-1163 . |
| MLA | Liu, Genggeng et al. "Rapid Single-Flux-Quantum Circuit Routing Algorithm Considering Length Matching" . | Computer Research and Development 62 . 5 (2025) : 1151-1163 . |
| APA | Liu, Genggeng , Yu, Yantao , Zhou, Ruping , Wei, Rongshan , Xu, Ning . Rapid Single-Flux-Quantum Circuit Routing Algorithm Considering Length Matching . | Computer Research and Development , 2025 , 62 (5) , 1151-1163 . |
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由于快速单通量量子(rapid single-flux-quantum,RSFQ)电路的高频特性,对电路的版图设计构成了巨大挑战.针对RSFQ电路的高频特性带来的电路时延问题,可以在布线阶段通过使用延时元件如无源传输线来解决.因为无源传输线的时延与它的长度近似成正比,且传输线的功耗不随着线长增加而增大,所以对于快速单通量量子电路而言长度匹配布线是一个非常重要的问题.为此,提出了一种高效的考虑长度匹配的RSFQ电路布线算法,包括3个关键策略:1)在生成初始路径时,提出了一种迂回布线的方法,在不改变初始布线空间的情况下,满足无源传输线的部分长度匹配;2)提出了一种基于区域感知的迭代资源插入策略,减少需要添加的额外资源区域;3)提出了一种考虑阻塞代价的长度匹配驱动布线策略,提高了对布线空间的资源利用.实验结果表明所提算法与现有的多端布线算法相比,布线所需的区域面积减少了 8％,运行时间减少了 36％,从而取得快速且高质量的布线结果.
Keyword ：
快速单通量量子电路 快速单通量量子电路 时序匹配 时序匹配 物理设计 物理设计 通道布线 通道布线 长度匹配 长度匹配
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| GB/T 7714 | 刘耿耿 , 余延涛 , 周茹平 et al. 考虑长度匹配的快速单通量量子电路布线算法 [J]. | 计算机研究与发展 , 2025 , 62 (5) : 1151-1163 . |
| MLA | 刘耿耿 et al. "考虑长度匹配的快速单通量量子电路布线算法" . | 计算机研究与发展 62 . 5 (2025) : 1151-1163 . |
| APA | 刘耿耿 , 余延涛 , 周茹平 , 魏榕山 , 徐宁 . 考虑长度匹配的快速单通量量子电路布线算法 . | 计算机研究与发展 , 2025 , 62 (5) , 1151-1163 . |
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This paper presents a cascode OTA assisted by a floating inverter amplifier, which offers high gain with reduced power consumption and excellent linearity. In comparison to conventional cascode OTA, it achieves approximately 30 % power savings while maintaining the same level of linearity. To address the limited output swing of the cascode OTA, the finite impulse response (FIR) DAC technique, which is widely used in CTDSM, is introduced in the DTDSM. The FIR DAC output resembles that of a multibit DAC without requiring a mismatch shaping circuit. By incorporating FIR DAC, we effectively scale up integrator coefficients and decrease power consumption of the first-stage integrator. A prototype was fabricated in a 0.18-mu m CMOS process with an active area of 0.2 mm2, achieving peak SNDR/DR values of 94.5 and 96.5 dB while consuming only 190 mu W of power.
Keyword ：
Analog -to -digital converter (ADC) Analog -to -digital converter (ADC) Assisted OTA Assisted OTA Delta -sigma modulator Delta -sigma modulator Finite impulse response Finite impulse response Floating inverter amplifier Floating inverter amplifier
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| GB/T 7714 | Huang, Gongxing , Wei, Cong , Wei, Rongshan . A 94.5-dB SNDR 96.5-dB DR discrete-time delta-sigma modulator using FIA assisted OTA and FIR DAC feedback [J]. | MICROELECTRONICS JOURNAL , 2024 , 150 . |
| MLA | Huang, Gongxing et al. "A 94.5-dB SNDR 96.5-dB DR discrete-time delta-sigma modulator using FIA assisted OTA and FIR DAC feedback" . | MICROELECTRONICS JOURNAL 150 (2024) . |
| APA | Huang, Gongxing , Wei, Cong , Wei, Rongshan . A 94.5-dB SNDR 96.5-dB DR discrete-time delta-sigma modulator using FIA assisted OTA and FIR DAC feedback . | MICROELECTRONICS JOURNAL , 2024 , 150 . |
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The next-generation computing system is required to perform 10(18) floating point operations per second to address the exponential growth of data from sensory terminals, driven by advancements in artificial intelligence and the Internet of Things. Even if a supercomputer possesses the capability to execute these operations, managing heat dissipation becomes a significant challenge when the electronic synapse array reaches a comparable scale with the human neuron network. One potential solution to address thermal hotspots in electronic devices is the use of vertically-aligned hexagonal boron nitride (h-BN) known for its high thermal conductivity. In this study, we have developed textured h-BN films using the high power impulse magnetron sputtering technique. The thermal conductivity of the oriented h-BN film is approximately 354% higher than that of the randomly oriented counterpart. By fabricating electronic synapses based on the textured h-BN thin film, we demonstrate various bio-synaptic plasticity in this device. Our results indicate that orientation engineering can effectively enable h-BN to function as a suitable self-heat dissipation layer, thereby paving the way for future wearable memory devices, solar cells, and neuromorphic devices.
Keyword ：
boron nitride boron nitride high thermal conductivity high thermal conductivity low-power memory low-power memory neuromorphic computing neuromorphic computing vertically-aligned vertically-aligned
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| GB/T 7714 | Zhang, Haizhong , Ju, Xin , Jiang, Haitao et al. Implementation of high thermal conductivity and synaptic metaplasticity in vertically-aligned hexagonal boron nitride-based memristor [J]. | SCIENCE CHINA-MATERIALS , 2024 , 67 (6) : 1907-1914 . |
| MLA | Zhang, Haizhong et al. "Implementation of high thermal conductivity and synaptic metaplasticity in vertically-aligned hexagonal boron nitride-based memristor" . | SCIENCE CHINA-MATERIALS 67 . 6 (2024) : 1907-1914 . |
| APA | Zhang, Haizhong , Ju, Xin , Jiang, Haitao , Yang, Dan , Wei, Rongshan , Hu, Wei et al. Implementation of high thermal conductivity and synaptic metaplasticity in vertically-aligned hexagonal boron nitride-based memristor . | SCIENCE CHINA-MATERIALS , 2024 , 67 (6) , 1907-1914 . |
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Conventional sense amplifiers limit the performance of current RRAM computing-in-memory (CIM) macro circuits, resulting in high latency and energy consumption. This paper introduces a multi-bit quantization technology low-latency voltage sense amplifier (MQL-VSA). Firstly, the multi-bit quantization technology enhances circuit quantization efficiency, reducing the number of operational states in conventional VSA. Secondly, by simplifying the sequential logic circuits in conventional VSA, the complexity of sequential control signals is reduced, further diminishing readout latency. Experimental results demonstrate that the MQL-VSA achieves a 1.40-times decrease in readout latency and a 1.28-times reduction in power consumption compared to conventional VSA. Additionally, an 8-bit input, 8-bit weight, 14-bit output macro circuit utilizing MQL-VSA exhibited a 1.11times latency reduction and 1.04-times energy savings.
Keyword ：
computing-in-memory computing-in-memory low latency low latency RRAM RRAM voltage sense amplifier voltage sense amplifier
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| GB/T 7714 | Hu, Wei , Zhang, Hangze , Wei, Rongshan et al. A Multi-Bit Quantization Low-Latency Voltage Sense Amplifier Applied in RRAM Computing-in-Memory Macro Circuits [J]. | ELECTRONICS , 2024 , 13 (2) . |
| MLA | Hu, Wei et al. "A Multi-Bit Quantization Low-Latency Voltage Sense Amplifier Applied in RRAM Computing-in-Memory Macro Circuits" . | ELECTRONICS 13 . 2 (2024) . |
| APA | Hu, Wei , Zhang, Hangze , Wei, Rongshan , Chen, Qunchao . A Multi-Bit Quantization Low-Latency Voltage Sense Amplifier Applied in RRAM Computing-in-Memory Macro Circuits . | ELECTRONICS , 2024 , 13 (2) . |
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This paper presents a low-power, high-gain integrator design that uses a cascode operational transconductance amplifier (OTA) with floating inverter-amplifier (FIA) assistance. Compared to a traditional cascode, the proposed integrator can achieve a gain of 80 dB, while reducing power consumption by 30%. Upon completing the analysis, the value of the FIA drive capacitor and clock scheme for the FIA-assisted OTA were obtained. To enhance the dynamic range (DR) and mitigate quantization noise, a tri-level quantizer was employed. The design of the feedback digital-to-analog converter (DAC) was simplified, as it does not use additional mismatch shaping techniques. A third-order, discrete-time delta-sigma modulator was designed and fabricated in a 0.18 mu m complementary metal-oxide semiconductor (CMOS) process. It operated on a 1.8 V supply, consuming 221 mu W with a 24 kHz bandwidth. The measured SNDR and DR were 90.9 dB and 95.3 dB, respectively.
Keyword ：
analog-to-digital conversion analog-to-digital conversion audio audio delta-sigma modulator delta-sigma modulator discrete-time discrete-time floating inverter-amplifier floating inverter-amplifier
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| GB/T 7714 | Huang, Gongxing , Wei, Cong , Wei, Rongshan . A 90.9 dB SNDR 95.3 dB DR Audio Delta-Sigma Modulator with FIA-Assisted OTA [J]. | SENSORS , 2024 , 24 (5) . |
| MLA | Huang, Gongxing et al. "A 90.9 dB SNDR 95.3 dB DR Audio Delta-Sigma Modulator with FIA-Assisted OTA" . | SENSORS 24 . 5 (2024) . |
| APA | Huang, Gongxing , Wei, Cong , Wei, Rongshan . A 90.9 dB SNDR 95.3 dB DR Audio Delta-Sigma Modulator with FIA-Assisted OTA . | SENSORS , 2024 , 24 (5) . |
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This article presents a dynamic range (DR) enhanced discrete-time delta-sigma modulator (DTDSM) applied to the Internet of Things (IoT). It is based on an asynchronous 1.5 -bit successive-approximation-resister (SAR) quantizer and a tri-level feedback capacitive digital -to -analog converter (CDAC), eliminating the dynamic element matching (DEM) overhead. The proposed DR enhancement (DRE) technique based on a variable threshold (VTH) allows the system to achieve maximum benefits at different input amplitudes. The system is configured in a high loop gain mode at small input amplitudes, providing the system with a stronger noise-shaping (NS) capability. The system is configured in the maximum stable amplitude (MSA) mode for large input amplitudes. In addition, we modified the working model of the cascoded floating inverter amplifier (FIA) in the weak inversion region. The prototype DTDSM is implemented in a 180-nm CMOS process, achieving a 94.7 -dB DR and 92.4 -dB signal-to-noise-and-distortion ratio (SNDR) at a 700 -Hz bandwidth with only 2.3-mu W power consumption. As a result, the Schreier figure-of-merit (FoM) for SNDR and DR is 177.2 and 179.5 dB, respectively.
Keyword ：
Analog-to-digital converter (ADC) Analog-to-digital converter (ADC) cascoded floating inverter amplifier (FIA) cascoded floating inverter amplifier (FIA) discrete-time delta-sigma modulator (DTDSM) discrete-time delta-sigma modulator (DTDSM) dynamic range enhancement (DRE) dynamic range enhancement (DRE) tri-level capacitive digital-to-analog converter (CDAC) tri-level capacitive digital-to-analog converter (CDAC)
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| GB/T 7714 | Wei, Cong , Wei, Rongshan , Huang, Lijie et al. An Energy-Efficient Discrete-Time Delta–Sigma Modulator With Dynamic-Range Enhancement and Tri-Level CDAC [J]. | IEEE JOURNAL OF SOLID-STATE CIRCUITS , 2024 , 59 (9) : 2848-2857 . |
| MLA | Wei, Cong et al. "An Energy-Efficient Discrete-Time Delta–Sigma Modulator With Dynamic-Range Enhancement and Tri-Level CDAC" . | IEEE JOURNAL OF SOLID-STATE CIRCUITS 59 . 9 (2024) : 2848-2857 . |
| APA | Wei, Cong , Wei, Rongshan , Huang, Lijie , Huang, Gongxing , Lai, Jinze , Tan, Zhichao . An Energy-Efficient Discrete-Time Delta–Sigma Modulator With Dynamic-Range Enhancement and Tri-Level CDAC . | IEEE JOURNAL OF SOLID-STATE CIRCUITS , 2024 , 59 (9) , 2848-2857 . |
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