Query：
学者姓名：魏榕山
Refining：
Year
Type
Indexed by
Source
Complex
Former Name
Co-
Language
Clean All
Abstract ：
热释电红外技术已广泛应用于交通出行和智能家居等领域。用于接收、放大、处理热释电红外传感器输入信号的控制芯片的优劣，是衡量热释电红外产品性能的重要标准。设计出一款用于照明控制、防盗报警等领域的热释电红外控制芯片。该芯片是一款基于5 V 1P3M CMOS工艺的低静态功耗、芯片面积小的热释电红外控制芯片，只有8个引脚，外围器件少，可与传感器合封，具有小型化，能有效抑制手机、Wi-Fi等射频干扰的优势。仿真结果表明，芯片的静态功耗小于20μA，动态功耗小于1 mA，在3.0～5.5 V电压范围内能正常工作，有效面积约为0.309 mm2。
Keyword ：
带隙基准电流源 带隙基准电流源 模数转换器 模数转换器 灵敏度可调 灵敏度可调 热释电红外 热释电红外 环形振荡器 环形振荡器
Cite：
Copy from the list or Export to your reference management。
| GB/T 7714 | 吴航杰 , 钟晟 , 魏榕山 . 一种热释电红外控制芯片设计 [J]. | 电视技术 , 2024 , 48 (03) : 65-70,74 . |
| MLA | 吴航杰 等. "一种热释电红外控制芯片设计" . | 电视技术 48 . 03 (2024) : 65-70,74 . |
| APA | 吴航杰 , 钟晟 , 魏榕山 . 一种热释电红外控制芯片设计 . | 电视技术 , 2024 , 48 (03) , 65-70,74 . |
| Export to | NoteExpress RIS BibTex |
Version ：
Abstract ：
Conventional sense amplifiers limit the performance of current RRAM computing-in-memory (CIM) macro circuits, resulting in high latency and energy consumption. This paper introduces a multi-bit quantization technology low-latency voltage sense amplifier (MQL-VSA). Firstly, the multi-bit quantization technology enhances circuit quantization efficiency, reducing the number of operational states in conventional VSA. Secondly, by simplifying the sequential logic circuits in conventional VSA, the complexity of sequential control signals is reduced, further diminishing readout latency. Experimental results demonstrate that the MQL-VSA achieves a 1.40-times decrease in readout latency and a 1.28-times reduction in power consumption compared to conventional VSA. Additionally, an 8-bit input, 8-bit weight, 14-bit output macro circuit utilizing MQL-VSA exhibited a 1.11times latency reduction and 1.04-times energy savings.
Keyword ：
computing-in-memory computing-in-memory low latency low latency RRAM RRAM voltage sense amplifier voltage sense amplifier
Cite：
Copy from the list or Export to your reference management。
| GB/T 7714 | Hu, Wei , Zhang, Hangze , Wei, Rongshan et al. A Multi-Bit Quantization Low-Latency Voltage Sense Amplifier Applied in RRAM Computing-in-Memory Macro Circuits [J]. | ELECTRONICS , 2024 , 13 (2) . |
| MLA | Hu, Wei et al. "A Multi-Bit Quantization Low-Latency Voltage Sense Amplifier Applied in RRAM Computing-in-Memory Macro Circuits" . | ELECTRONICS 13 . 2 (2024) . |
| APA | Hu, Wei , Zhang, Hangze , Wei, Rongshan , Chen, Qunchao . A Multi-Bit Quantization Low-Latency Voltage Sense Amplifier Applied in RRAM Computing-in-Memory Macro Circuits . | ELECTRONICS , 2024 , 13 (2) . |
| Export to | NoteExpress RIS BibTex |
Version ：
Abstract ：
This paper presents a low-power, high-gain integrator design that uses a cascode operational transconductance amplifier (OTA) with floating inverter-amplifier (FIA) assistance. Compared to a traditional cascode, the proposed integrator can achieve a gain of 80 dB, while reducing power consumption by 30%. Upon completing the analysis, the value of the FIA drive capacitor and clock scheme for the FIA-assisted OTA were obtained. To enhance the dynamic range (DR) and mitigate quantization noise, a tri-level quantizer was employed. The design of the feedback digital-to-analog converter (DAC) was simplified, as it does not use additional mismatch shaping techniques. A third-order, discrete-time delta-sigma modulator was designed and fabricated in a 0.18 mu m complementary metal-oxide semiconductor (CMOS) process. It operated on a 1.8 V supply, consuming 221 mu W with a 24 kHz bandwidth. The measured SNDR and DR were 90.9 dB and 95.3 dB, respectively.
Keyword ：
analog-to-digital conversion analog-to-digital conversion audio audio delta-sigma modulator delta-sigma modulator discrete-time discrete-time floating inverter-amplifier floating inverter-amplifier
Cite：
Copy from the list or Export to your reference management。
| GB/T 7714 | Huang, Gongxing , Wei, Cong , Wei, Rongshan . A 90.9 dB SNDR 95.3 dB DR Audio Delta-Sigma Modulator with FIA-Assisted OTA [J]. | SENSORS , 2024 , 24 (5) . |
| MLA | Huang, Gongxing et al. "A 90.9 dB SNDR 95.3 dB DR Audio Delta-Sigma Modulator with FIA-Assisted OTA" . | SENSORS 24 . 5 (2024) . |
| APA | Huang, Gongxing , Wei, Cong , Wei, Rongshan . A 90.9 dB SNDR 95.3 dB DR Audio Delta-Sigma Modulator with FIA-Assisted OTA . | SENSORS , 2024 , 24 (5) . |
| Export to | NoteExpress RIS BibTex |
Version ：
Abstract ：
This article presents a dynamic range (DR) enhanced discrete-time delta-sigma modulator (DTDSM) applied to the Internet of Things (IoT). It is based on an asynchronous 1.5 -bit successive-approximation-resister (SAR) quantizer and a tri-level feedback capacitive digital -to -analog converter (CDAC), eliminating the dynamic element matching (DEM) overhead. The proposed DR enhancement (DRE) technique based on a variable threshold (VTH) allows the system to achieve maximum benefits at different input amplitudes. The system is configured in a high loop gain mode at small input amplitudes, providing the system with a stronger noise-shaping (NS) capability. The system is configured in the maximum stable amplitude (MSA) mode for large input amplitudes. In addition, we modified the working model of the cascoded floating inverter amplifier (FIA) in the weak inversion region. The prototype DTDSM is implemented in a 180-nm CMOS process, achieving a 94.7 -dB DR and 92.4 -dB signal-to-noise-and-distortion ratio (SNDR) at a 700 -Hz bandwidth with only 2.3-mu W power consumption. As a result, the Schreier figure-of-merit (FoM) for SNDR and DR is 177.2 and 179.5 dB, respectively.
Keyword ：
Analog-to-digital converter (ADC) Analog-to-digital converter (ADC) cascoded floating inverter amplifier (FIA) cascoded floating inverter amplifier (FIA) discrete-time delta-sigma modulator (DTDSM) discrete-time delta-sigma modulator (DTDSM) dynamic range enhancement (DRE) dynamic range enhancement (DRE) tri-level capacitive digital-to-analog converter (CDAC) tri-level capacitive digital-to-analog converter (CDAC)
Cite：
Copy from the list or Export to your reference management。
| GB/T 7714 | Wei, Cong , Wei, Rongshan , Huang, Lijie et al. An Energy-Efficient Discrete-Time Delta–Sigma Modulator With Dynamic-Range Enhancement and Tri-Level CDAC [J]. | IEEE JOURNAL OF SOLID-STATE CIRCUITS , 2024 . |
| MLA | Wei, Cong et al. "An Energy-Efficient Discrete-Time Delta–Sigma Modulator With Dynamic-Range Enhancement and Tri-Level CDAC" . | IEEE JOURNAL OF SOLID-STATE CIRCUITS (2024) . |
| APA | Wei, Cong , Wei, Rongshan , Huang, Lijie , Huang, Gongxing , Lai, Jinze , Tan, Zhichao . An Energy-Efficient Discrete-Time Delta–Sigma Modulator With Dynamic-Range Enhancement and Tri-Level CDAC . | IEEE JOURNAL OF SOLID-STATE CIRCUITS , 2024 . |
| Export to | NoteExpress RIS BibTex |
Version ：
Abstract ：
The next-generation computing system is required to perform 1018 floating point operations per second to address the exponential growth of data from sensory terminals, driven by advancements in artificial intelligence and the Internet of Things. Even if a supercomputer possesses the capability to execute these operations, managing heat dissipation becomes a significant challenge when the electronic synapse array reaches a comparable scale with the human neuron network. One potential solution to address thermal hotspots in electronic devices is the use of vertically-aligned hexagonal boron nitride (h-BN) known for its high thermal conductivity. In this study, we have developed textured h-BN films using the high power impulse magnetron sputtering technique. The thermal conductivity of the oriented h-BN film is approximately 354% higher than that of the randomly oriented counterpart. By fabricating electronic synapses based on the textured h-BN thin film, we demonstrate various bio-synaptic plasticity in this device. Our results indicate that orientation engineering can effectively enable h-BN to function as a suitable self-heat dissipation layer, thereby paving the way for future wearable memory devices, solar cells, and neuromorphic devices. (Figure presented.) © Science China Press 2024.
Keyword ：
Boron nitride Boron nitride Cell engineering Cell engineering Digital arithmetic Digital arithmetic III-V semiconductors III-V semiconductors Magnetron sputtering Magnetron sputtering Nitrides Nitrides Supercomputers Supercomputers Textures Textures Thin films Thin films
Cite：
Copy from the list or Export to your reference management。
| GB/T 7714 | Zhang, Haizhong , Ju, Xin , Jiang, Haitao et al. Implementation of high thermal conductivity and synaptic metaplasticity in vertically-aligned hexagonal boron nitride-based memristor [J]. | Science China Materials , 2024 , 67 (6) : 1907-1914 . |
| MLA | Zhang, Haizhong et al. "Implementation of high thermal conductivity and synaptic metaplasticity in vertically-aligned hexagonal boron nitride-based memristor" . | Science China Materials 67 . 6 (2024) : 1907-1914 . |
| APA | Zhang, Haizhong , Ju, Xin , Jiang, Haitao , Yang, Dan , Wei, Rongshan , Hu, Wei et al. Implementation of high thermal conductivity and synaptic metaplasticity in vertically-aligned hexagonal boron nitride-based memristor . | Science China Materials , 2024 , 67 (6) , 1907-1914 . |
| Export to | NoteExpress RIS BibTex |
Version ：
Abstract ：
本发明涉及一种具有单点校准的带隙基准电压源。利用纹波检测电路和斩波技术将运算放大器中的失配转换成纹波进行消除。而其余器件的失配由修调DAC进行单点修调，完成对工艺偏差的校准。这大大提高了带隙基准电压源输出电压的精度。该发明在高精度带隙基准电压源领域中，应用前景十分广阔。
Cite：
Copy from the list or Export to your reference management。
| GB/T 7714 | 魏榕山 , 林方俊 , 赵固猛 . 一种具有单点校准的带隙基准电压源 : CN202210710954.6[P]. | 2022-06-22 00:00:00 . |
| MLA | 魏榕山 et al. "一种具有单点校准的带隙基准电压源" : CN202210710954.6. | 2022-06-22 00:00:00 . |
| APA | 魏榕山 , 林方俊 , 赵固猛 . 一种具有单点校准的带隙基准电压源 : CN202210710954.6. | 2022-06-22 00:00:00 . |
| Export to | NoteExpress RIS BibTex |
Version ：
Abstract ：
A voltage reference is indispensable in Integrated Circuits. To improve the limited linear output voltage range and energy efficiency of a voltage reference, we innovatively propose a switched-capacitor-based programmable voltage reference scheme employing inverter-based OTAs to reduce the power consumption, simultaneously using a novel Correlated Level Shifting (CLS) technique (without active overhead) to enhance the OTA's DC gain and integral gain. Experimented with SMIC 180 nm CMOS technology, a scheme-based voltage reference realizes a programable output voltage range from 266 to 995 mV at -30 to 120 degrees C, and the corresponding temperature coefficient (TC) ranges from 82.4 to 99.5 ppm/degrees C. The power consumption is 976 nW. Furthermore, comparative experiments and evaluations with other schemes have unequivocally verified the superiority of our proposed scheme, characterized by its high energy efficiency and wide output voltage range. The scheme can be suitably deployed in a multitude of novel edge-data processing systems.
Keyword ：
correlated level shifting correlated level shifting switched-capacitor switched-capacitor voltage reference voltage reference
Cite：
Copy from the list or Export to your reference management。
| GB/T 7714 | Wei, Rongshan , Chen, Chu , Wei, Cong et al. An Energy-Efficient Inverter-Based Voltage Reference Scheme with Wide Output Range Using Correlated Level Shifting Technique [J]. | ELECTRONICS , 2023 , 12 (24) . |
| MLA | Wei, Rongshan et al. "An Energy-Efficient Inverter-Based Voltage Reference Scheme with Wide Output Range Using Correlated Level Shifting Technique" . | ELECTRONICS 12 . 24 (2023) . |
| APA | Wei, Rongshan , Chen, Chu , Wei, Cong , Wang, Renping , Huang, Lijie , Zhou, Qikun et al. An Energy-Efficient Inverter-Based Voltage Reference Scheme with Wide Output Range Using Correlated Level Shifting Technique . | ELECTRONICS , 2023 , 12 (24) . |
| Export to | NoteExpress RIS BibTex |
Version ：
Abstract ：
This study presents a dynamic amplifier with high energy efficiency and high gain suitable for a delta-sigma modulator based on the floating-inverter amplifier (FIA), in-depth analysis of the existing FIA and its improved structure, and simulation verification. Compared with other FIA structures, the proposed amplifier has a better compromise in terms of power consumption and stability, which was designed and simulated using the SMIC 180 nm CMOS technology. Under a 1.2 V power supply, the closed-loop direct current (DC) gain and the output swing were about 104 dB and +/- 380 mV, respectively, and the input-referred in-band noise was about -100 dB with the chopper circuit.
Cite：
Copy from the list or Export to your reference management。
| GB/T 7714 | Lai, Jinze , Lin, Yuxuan , Zhao, Gumeng et al. Analysis and Design of High-Energy-Efficiency Amplifiers for Delta-Sigma Modulators [J]. | ACTIVE AND PASSIVE ELECTRONIC COMPONENTS , 2023 , 2023 . |
| MLA | Lai, Jinze et al. "Analysis and Design of High-Energy-Efficiency Amplifiers for Delta-Sigma Modulators" . | ACTIVE AND PASSIVE ELECTRONIC COMPONENTS 2023 (2023) . |
| APA | Lai, Jinze , Lin, Yuxuan , Zhao, Gumeng , Huang, Lijie , Wei, Cong , Wei, Rongshan et al. Analysis and Design of High-Energy-Efficiency Amplifiers for Delta-Sigma Modulators . | ACTIVE AND PASSIVE ELECTRONIC COMPONENTS , 2023 , 2023 . |
| Export to | NoteExpress RIS BibTex |
Version ：
Abstract ：
This paper introduces a discrete-time delta-sigma ADC for the Internet of Things (IoT) applications. It utilizes second-order 4-bit successive approximation register (SAR) quantizer architecture based on the oversampling technique to ensure a sufficiently high SQNR. Additionally, dynamic weighted averaging (DWA) technique is employed to achieve good feedback CDAC linearity. System-level analysis and circuit implementation analysis are introduced in detail. The implemented prototype of this architecture is manufactured using a 180 nm CMOS process. The proposed ADC, operating at a supply voltage of 1.8 V and a sampling frequency of 2.5 MHz, including biasing circuitry, consumes a total power of 1.3 mW. This ADC achieves a DR of 102.6 dB, SNR of 101.5 dB, and SNDR of 98.6 dB within a 10 kHz bandwidth. As a result, the Schreier figure-of-merits (FoM) for SNR, SNDR and DR is 167.46 dB, 170.36 dB, and 171.46 dB.
Keyword ：
Delta -sigma Delta -sigma Discrete -time Discrete -time Internet of Things (IoT) Internet of Things (IoT) SAR quantizer SAR quantizer
Cite：
Copy from the list or Export to your reference management。
| GB/T 7714 | Wei, Cong , Chen, Chengying , Huang, Gongxing et al. A 1.8 V 98.6 dB SNDR discrete-time CMOS delta-sigma ADC [J]. | MICROELECTRONICS JOURNAL , 2023 , 144 . |
| MLA | Wei, Cong et al. "A 1.8 V 98.6 dB SNDR discrete-time CMOS delta-sigma ADC" . | MICROELECTRONICS JOURNAL 144 (2023) . |
| APA | Wei, Cong , Chen, Chengying , Huang, Gongxing , Huang, Lijie , Wang, Renping , Wei, Rongshan . A 1.8 V 98.6 dB SNDR discrete-time CMOS delta-sigma ADC . | MICROELECTRONICS JOURNAL , 2023 , 144 . |
| Export to | NoteExpress RIS BibTex |
Version ：
Abstract ：
A broadband and CMOS-compatible polarization beam splitter and rotator (PSR) built on the silicon nitride -on-silicon multilayer platform is presented. The PSR is realized by cascading a polarization beam splitter and a polarization rotator, which are both subtly constructed with an asymmetrical directional coupler waveguide struc-ture. The advantage of this device is that the function of PSR can be directly realized in the SiN layer, providing a promising solution to the polarization diversity schemes in SiN photonic circuits. The chip is expected to have high power handling capability as the light is input from the SiN waveguide. The use of silicon dioxide as the upper cladding of the device ensures its compatibility with the metal back-end-of-line process. By optimizing the struc-ture parameters, a polarization conversion loss lower than 1 dB and cross talk larger than 27.6 dB can be obtained for TM-TE mode conversion over a wavelength range of 1450 to 1600 nm. For TE mode, the insertion loss is lower than 0.26 dB and cross talk is larger than 25.3 dB over the same wavelength range. The proposed device has good potential in diversifying the functionalities of the multilayer photonic chip with high integration density.(c) 2023 Optica Publishing Group
Cite：
Copy from the list or Export to your reference management。
| GB/T 7714 | Wang, Linghua , Peng, Hejie , Zheng, Langteng et al. Broadband and CMOS-compatible polarization splitter and rotator built on a silicon nitride-on-silicon multilayer platform [J]. | APPLIED OPTICS , 2023 , 62 (4) : 1046-1056 . |
| MLA | Wang, Linghua et al. "Broadband and CMOS-compatible polarization splitter and rotator built on a silicon nitride-on-silicon multilayer platform" . | APPLIED OPTICS 62 . 4 (2023) : 1046-1056 . |
| APA | Wang, Linghua , Peng, Hejie , Zheng, Langteng , Chen, Huaixi , Zhang, Yazhen , Huang, Jiwei et al. Broadband and CMOS-compatible polarization splitter and rotator built on a silicon nitride-on-silicon multilayer platform . | APPLIED OPTICS , 2023 , 62 (4) , 1046-1056 . |
| Export to | NoteExpress RIS BibTex |
Version ：
Export
| Results： |
Selected to |
| Format： |
