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学者姓名：张栋
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Radio access network (RAN) enables large-scale collection of sensitive data. Privacy-preserving techniques aim to learn knowledge from sensitive data to improve services without compromising privacy. However, as the data scale increases, enforcing privacy-preserving techniques on sensitive data may consume a considerable amount of system resources and impose performance penalties. To reduce system resource consumption, we present NetDP, an in-network architecture for privacy-preserving techniques by leveraging programmable switches to improve resource efficiency (i.e., CPU cycles, network bandwidth, and privacy budgets). The key idea of NetDP is to accommodate and exploit cryptographic operators to reduce resource consumption rather than repetitively and exhaustively suppressing the impact of these techniques. To the best of our knowledge, this is the first time that privacy-preserving techniques in a large-scale data processing system have been enforced on programmable switches. Our experiments based on Tofino switches indicate that NetDP significantly reduces computation latency (e.g., 40.2%-55.8% latency in computations) without impacting fidelity. IEEE
Keyword ：
Computer architecture Computer architecture Data processing Data processing differential privacy differential privacy Differential privacy Differential privacy In-network computing In-network computing Noise Noise Pipelines Pipelines Privacy Privacy Sensitivity Sensitivity
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| GB/T 7714 | Zhou, Z. , Chen, H. , Chen, L. et al. NetDP: In-Network Differential Privacy for Large-Scale Data Processing [J]. | IEEE Transactions on Green Communications and Networking , 2024 , 8 (3) : 1-1 . |
| MLA | Zhou, Z. et al. "NetDP: In-Network Differential Privacy for Large-Scale Data Processing" . | IEEE Transactions on Green Communications and Networking 8 . 3 (2024) : 1-1 . |
| APA | Zhou, Z. , Chen, H. , Chen, L. , Zhang, D. , Wu, C. , Liu, X. et al. NetDP: In-Network Differential Privacy for Large-Scale Data Processing . | IEEE Transactions on Green Communications and Networking , 2024 , 8 (3) , 1-1 . |
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Regular expression matching is pivotal in numerous network applications. With the ever-increasing scale of data center traffic, deploying regular expression matching modules on traditional servers struggles to meet throughput demands. Emerging programmable switches have brought new prospects for high-speed pattern matching. However, deploying regular expression matching onto programmable switches presents the challenge of space explosion incurred by compiling regular expressions into a Deterministic Finite Automata (DFA). In this paper, we introduce P4Rex, a regular expression matching system designed for programmable switches. P4Rex synergistically leverages two following techniques: an efficient regular expression grouping algorithm that partitions regular expressions into different groups to reduce memory consumption, and DFA compression technology to achieve transition sharing. Experimental results demonstrate that P4Rex exhibits an average improvement of 17% and maximum improvement of 30% on memory consumption compared to prior regular expression grouping schemes and saves more than 10x memory consumption compared to deploying DFA directly on programmable switch. © 2024 Elsevier B.V.
Keyword ：
Pattern matching Pattern matching Programmable data plane Programmable data plane Software-defined networking Software-defined networking
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| GB/T 7714 | Lin, J. , Lin, W. , Lin, H. et al. P4Rex: Accelerating regular expression matching with programmable switches [J]. | Computer Networks , 2024 , 252 . |
| MLA | Lin, J. et al. "P4Rex: Accelerating regular expression matching with programmable switches" . | Computer Networks 252 (2024) . |
| APA | Lin, J. , Lin, W. , Lin, H. , Zhu, L. , Zhang, D. , Wu, C. . P4Rex: Accelerating regular expression matching with programmable switches . | Computer Networks , 2024 , 252 . |
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The programmable switch offers a limited capacity of packet header vector (PHV) words that store packet header fields and metadata fields defined by network functions. However, existing switch compilers employ inefficient strategies of encoding fields on PHV words. Their encoding wastes scarce PHV words and may result in failures when deploying network functions. In this paper, we propose, a new framework that reuses PHV words for as many fields as possible to achieve resource-efficient PHV encoding. offers a field analyzer and an optimization framework. The analyzer identifies which fields can reuse PHV words while preserving the original packet processing logic. The framework integrates analysis results into its encoding to offer the resource-optimal decisions. Also, to achieve timeliness at runtime, it provides a Greedy-based heuristic, which quickly solves PHV encoding and returns near-optimal results. We evaluate with production-scale network functions. Our results show that reduces the consumption of PHV words by up to 85%. IEEE
Keyword ：
Encoding Encoding Metadata Metadata Optimization Optimization Packet header vector Packet header vector Production Production programmable switch programmable switch Program processors Program processors Runtime Runtime Vectors Vectors
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| GB/T 7714 | Chen, X. , Zhang, W. , Sun, X. et al. Resource-Efficient and Timely Packet Header Vector (PHV) Encoding on Programmable Switches [J]. | ACM Transactions on Networking , 2024 , 32 (5) : 1-16 . |
| MLA | Chen, X. et al. "Resource-Efficient and Timely Packet Header Vector (PHV) Encoding on Programmable Switches" . | ACM Transactions on Networking 32 . 5 (2024) : 1-16 . |
| APA | Chen, X. , Zhang, W. , Sun, X. , Liu, H. , Zhang, J. , Huang, Q. et al. Resource-Efficient and Timely Packet Header Vector (PHV) Encoding on Programmable Switches . | ACM Transactions on Networking , 2024 , 32 (5) , 1-16 . |
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The programmable switch offers a limited capacity of packet header vector (PHV) words that store packet header fields and metadata fields defined by network functions. However, existing switch compilers employ inefficient strategies of encoding fields on PHV words. Their encoding wastes scarce PHV words and may result in failures when deploying network functions. In this paper, we propose, a new framework that reuses PHV words for as many fields as possible to achieve resource-efficient PHV encoding. offers a field analyzer and an optimization framework. The analyzer identifies which fields can reuse PHV words while preserving the original packet processing logic. The framework integrates analysis results into its encoding to offer the resource-optimal decisions. Also, to achieve timeliness at runtime, it provides a Greedy-based heuristic, which quickly solves PHV encoding and returns near-optimal results. We evaluate with production-scale network functions. Our results show that reduces the consumption of PHV words by up to 85%.
Keyword ：
Encoding Encoding Metadata Metadata Optimization Optimization Packet header vector Packet header vector Production Production programmable switch programmable switch Program processors Program processors Runtime Runtime Vectors Vectors
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| GB/T 7714 | Chen, Xiang , Zhang, Wenbin , Sun, Xi et al. Resource-Efficient and Timely Packet Header Vector (PHV) Encoding on Programmable Switches [J]. | IEEE-ACM TRANSACTIONS ON NETWORKING , 2024 , 32 (5) : 4191-4206 . |
| MLA | Chen, Xiang et al. "Resource-Efficient and Timely Packet Header Vector (PHV) Encoding on Programmable Switches" . | IEEE-ACM TRANSACTIONS ON NETWORKING 32 . 5 (2024) : 4191-4206 . |
| APA | Chen, Xiang , Zhang, Wenbin , Sun, Xi , Liu, Hongyan , Zhang, Jianshan , Huang, Qun et al. Resource-Efficient and Timely Packet Header Vector (PHV) Encoding on Programmable Switches . | IEEE-ACM TRANSACTIONS ON NETWORKING , 2024 , 32 (5) , 4191-4206 . |
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灰色故障是指对生产网络产生细微影响的交换机故障. 然而，当这些轻微故障相互叠加或与新增故障叠加时，可能会导致整个生产网络的瘫痪. 因此，检测灰色故障对生产网络的稳定性至关重要. 传统解决方案关注的是在控制平面收集数据平面交换机中的流记录，并对其进行处理以检测灰色故障. 然而，此类解决方案存在着不足：（1）缓存和处理大量的流记录会引入庞大的资源开销；（2）较高的检测时延无法保证灰色故障检测的时效性. 近年来，可编程交换机的出现为灰色故障检测技术带来了新机遇：网络管理员可以将灰色故障检测算法部署运行至可编程交换机的线速ASIC流水线上，从而支持低开销、低时延、高精度的网内灰色故障检测技术. 本文针对基于可编程交换机的网内灰色故障检测技术进行综述，在对灰色故障的概念、普遍性及对生产网络的危害进行描述的基础上，分析与讨论了现有基于可编程交换机的网内灰色故障检测技术的研究现状与进展，详细介绍每项技术的工作原理及流程，搭建真实的实验平台评估各项技术的检测指标，在文末指出了现有技术所面临的问题与挑战.
Keyword ：
可编程交换机 可编程交换机 数据中心网络 数据中心网络 数据报丢失 数据报丢失 灰色故障检测 灰色故障检测 网内计算 网内计算 网络测量 网络测量
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| GB/T 7714 | 刘宏岩 , 张栋 , 吴春明 . 基于可编程交换机的网内灰色故障检测技术研究进展 [J]. | 电子学报 , 2024 . |
| MLA | 刘宏岩 et al. "基于可编程交换机的网内灰色故障检测技术研究进展" . | 电子学报 (2024) . |
| APA | 刘宏岩 , 张栋 , 吴春明 . 基于可编程交换机的网内灰色故障检测技术研究进展 . | 电子学报 , 2024 . |
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Network administrators usually realize network functions in data plane programs. They employ the network-wide program deployment that decomposes input programs into match-action tables (MATs) while deploying each MAT on a specific switch. Since MATs may be deployed on different switches, existing solutions propose the inter-switch coordination that uses the per-packet header space to deliver crucial packet processing information among switches. However, such coordination incurs non-trivial per-packet byte overhead, leading to end-to-end performance degradation. We propose, a framework that aims to minimize the per-packet byte overhead. The key idea is to formulate network-wide program deployment as a mixed-integer programming (MIP) problem with the objective of minimizing the per-packet byte overhead. Also, offers a greedy-based heuristic that solves the problem in a near-optimal and timely manner. We have implemented on Tofino switches. Compared to existing frameworks, decreases the per-packet byte overhead by 156 bytes while preserving end-to-end performance in terms of flow completion time and goodput.
Keyword ：
Control systems Control systems Degradation Degradation Indexes Indexes inter-switch coordination inter-switch coordination Metadata Metadata Optimization Optimization Program deployment Program deployment Research and development Research and development Synchronization Synchronization
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| GB/T 7714 | Chen, Xiang , Liu, Hongyan , Xiao, Qingjiang et al. Hermes: Low-Overhead Inter-Switch Coordination in Network-Wide Data Plane Program Deployment [J]. | IEEE-ACM TRANSACTIONS ON NETWORKING , 2024 , 32 (4) : 2842-2857 . |
| MLA | Chen, Xiang et al. "Hermes: Low-Overhead Inter-Switch Coordination in Network-Wide Data Plane Program Deployment" . | IEEE-ACM TRANSACTIONS ON NETWORKING 32 . 4 (2024) : 2842-2857 . |
| APA | Chen, Xiang , Liu, Hongyan , Xiao, Qingjiang , Huang, Qun , Zhang, Dong , Zhou, Haifeng et al. Hermes: Low-Overhead Inter-Switch Coordination in Network-Wide Data Plane Program Deployment . | IEEE-ACM TRANSACTIONS ON NETWORKING , 2024 , 32 (4) , 2842-2857 . |
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Regular expression matching is pivotal in numerous network applications. With the ever-increasing scale of data center traffic, deploying regular expression matching modules on traditional servers struggles to meet throughput demands. Emerging programmable switches have brought new prospects for high-speed pattern matching. However, deploying regular expression matching onto programmable switches presents the challenge of space explosion incurred by compiling regular expressions into a Deterministic Finite Automata (DFA). In this paper, we introduce P4Rex, a regular expression matching system designed for programmable switches. P4Rex synergistically leverages two following techniques: an efficient regular expression grouping algorithm that partitions regular expressions into different groups to reduce memory consumption, and DFA compression technology to achieve transition sharing. Experimental results demonstrate that P4Rex exhibits an average improvement of 17% and maximum improvement of 30% on memory consumption compared to prior regular expression grouping schemes and saves more than 10x memory consumption compared to deploying DFA directly on programmable switch.
Keyword ：
Pattern matching Pattern matching Programmable data plane Programmable data plane Software-defined networking Software-defined networking
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| GB/T 7714 | Lin, Jing , Lin, Weiwei , Lin, Hang et al. P4Rex: Accelerating regular expression matching with programmable switches [J]. | COMPUTER NETWORKS , 2024 , 252 . |
| MLA | Lin, Jing et al. "P4Rex: Accelerating regular expression matching with programmable switches" . | COMPUTER NETWORKS 252 (2024) . |
| APA | Lin, Jing , Lin, Weiwei , Lin, Hang , Zhu, Longlong , Zhang, Dong , Wu, Chunming . P4Rex: Accelerating regular expression matching with programmable switches . | COMPUTER NETWORKS , 2024 , 252 . |
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Gray failures are micro switch malfunctions that have a subtle impact on production networks. However, when these micro malfunctions are superimposed on each other or on a new malfunction, they can lead to paralysis of production networks. Thus, the detection of gray failures is essential to the stability of production networks. Prior methods focus on using the control plane to collect flow records from data plane switches and process them to detect packet loss. However, they fall short due to (1) their high resource overhead of handling with massive flow records and (2) non-trivial delays that result in out-of-date failure detection. Recently, the emergence of programmable switches provides a promising alternative solution: the detection of gray failures can be offloaded to line-rate switch ASIC pipelines, enabling low-cost, low-latency, and high-accuracy in-network gray failure detection. This paper presents an illustrative survey of programmable switch-assisted techniques in in-network gray failure detection. First, we describe the concept of gray failures, their prevalence, and their impact to production networks. Second, we analyze and discuss the characteristics of state-of-the-art gray failures detection techniques built on programmable switches. Third, we illustrate the principle and workflow of each detection technique. Fourth, we conduct a real-world testbed to evaluate the metrics of each detection technique. Finally, we highlight the problems and challenges faced by existing techniques. © 2024 Chinese Institute of Electronics. All rights reserved.
Keyword ：
datacenter networks datacenter networks gray failure detection gray failure detection in-network computing in-network computing network measurement network measurement packet loss packet loss programmable switches programmable switches
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| GB/T 7714 | Liu, H.-Y. , Zhang, D. , Wu, C.-M. . Empowering In-Network Gray Failure Detection with Programmable Switches; [基于可编程交换机的网内灰色故障检测技术研究进展] [J]. | Acta Electronica Sinica , 2024 , 52 (10) : 3613-3622 . |
| MLA | Liu, H.-Y. et al. "Empowering In-Network Gray Failure Detection with Programmable Switches; [基于可编程交换机的网内灰色故障检测技术研究进展]" . | Acta Electronica Sinica 52 . 10 (2024) : 3613-3622 . |
| APA | Liu, H.-Y. , Zhang, D. , Wu, C.-M. . Empowering In-Network Gray Failure Detection with Programmable Switches; [基于可编程交换机的网内灰色故障检测技术研究进展] . | Acta Electronica Sinica , 2024 , 52 (10) , 3613-3622 . |
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Radio access network (RAN) enables large-scale collection of sensitive data. Privacy-preserving techniques aim to learn knowledge from sensitive data to improve services without compromising privacy. However, as the data scale increases, enforcing privacy-preserving techniques on sensitive data may consume a considerable amount of system resources and impose performance penalties. To reduce system resource consumption, we present NetDP, an in-network architecture for privacy-preserving techniques by leveraging programmable switches to improve resource efficiency (i.e., CPU cycles, network bandwidth, and privacy budgets). The key idea of NetDP is to accommodate and exploit cryptographic operators to reduce resource consumption rather than repetitively and exhaustively suppressing the impact of these techniques. To the best of our knowledge, this is the first time that privacy-preserving techniques in a large-scale data processing system have been enforced on programmable switches. Our experiments based on Tofino switches indicate that NetDP significantly reduces computation latency (e.g., 40.2%-55.8% latency in computations) without impacting fidelity.
Keyword ：
Computer architecture Computer architecture Data processing Data processing differential privacy differential privacy Differential privacy Differential privacy In-network computing In-network computing Noise Noise Pipelines Pipelines Privacy Privacy Sensitivity Sensitivity
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| GB/T 7714 | Zhou, Zhengyan , Chen, Hanze , Chen, Lingfei et al. NetDP: In-Network Differential Privacy for Large-Scale Data Processing [J]. | IEEE TRANSACTIONS ON GREEN COMMUNICATIONS AND NETWORKING , 2024 , 8 (3) : 1076-1089 . |
| MLA | Zhou, Zhengyan et al. "NetDP: In-Network Differential Privacy for Large-Scale Data Processing" . | IEEE TRANSACTIONS ON GREEN COMMUNICATIONS AND NETWORKING 8 . 3 (2024) : 1076-1089 . |
| APA | Zhou, Zhengyan , Chen, Hanze , Chen, Lingfei , Zhang, Dong , Wu, Chunming , Liu, Xuan et al. NetDP: In-Network Differential Privacy for Large-Scale Data Processing . | IEEE TRANSACTIONS ON GREEN COMMUNICATIONS AND NETWORKING , 2024 , 8 (3) , 1076-1089 . |
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Data center networks will elevate link bandwidth to over 200Gbps to meet the performance demands of distributed ML and NVMe. That means more traffic will be transmitted within one RTT, making the workload more burst. The challenge posed to congestion control (CC) is that there is barely enough time to make correct decisions. Sub-RTT, a method for switches to proactively generate congestion signals, reduces feedback delays, enhancing CC to handle burst traffic. However, Sub-RTT increases the sensitivity of the sender to queuing in switch buffers, thus leading to issues such as overreactions and link oscillations. We identified that utilizing fine-grained congestion signals and refining congestion stages to adjust congestion control decisions accordingly is key to solving the overreaction problem. In this paper, we propose FCC, a CC algorithm capable of swiftly addressing congestion with Sub-RTT while preventing overreactions in burst workload, thus achieving ultra-low latency and maintaining high link throughput. FCC utilizes programmable data planes to gather fine-grained congestion information through in-band network telemetry (INT), deploys bitmap-based snapshots on switches for real-time congestion stage identification, and dynamically allocates decisions. Extensive simulation experiments indicate that, compared to HPCC, FCC reduces the peak buffer occupancy on bottleneck switches by a factor of 3.2. In large-scale cluster simulations, FCC, when compared to HPCC and DCQCN, respectively, reduces the 99-th-percentile flow completion time of short flows by 39.2% and 128.2%. © 2024 IEEE.
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| GB/T 7714 | Chen, H. , Zhou, J. , Chen, X. et al. FCC: Fast Source Congestion Control for Ultra-Low Latency in Data Center Networks [未知]. |
| MLA | Chen, H. et al. "FCC: Fast Source Congestion Control for Ultra-Low Latency in Data Center Networks" [未知]. |
| APA | Chen, H. , Zhou, J. , Chen, X. , Cai, J. , Zhu, L. , Liu, H. et al. FCC: Fast Source Congestion Control for Ultra-Low Latency in Data Center Networks [未知]. |
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