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学者姓名：李凡阳
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Abstract ：
A direct bidirectional current discharge path between the input/output (I/O) and ground (GND) is essential for the robust protection of charging device models (CDM) in the tightly constrained design parameters of advanced low-voltage (LV) processes. Dual-direction silicon controlled rectifiers (DDSCRs) serve as ESD protection devices with high efficiency unit area discharge, enabling bidirectional electrostatic protection. However, the high trigger voltage of conventional DDSCR makes it unsuitable for ASICs used for the preamplification of biomedical signals, which only operate at low supply voltage. To address this issue, a self-biased triggered DDSCR (STDDSCR) structure is proposed to further reduce the trigger voltage. When the ESD pulse comes, the external RC trigger circuit controls the PMOS turn-on by self-bias, and the current release path is opened in advance to reduce the trigger voltage. As the ESD pulse voltage increases, the SCR loop opens to establish positive feedback and drain the amplified current. Additionally, the junction capacitance is decreased through high-resistance epitaxy and low-concentration P-well injection to further lower the trigger voltage. The simulation results of LTspice and TCAD respectively demonstrate that ESD devices can clamp transient high voltages earlier, with low parasitic capacitance and leakage current suitable for ESD protection of high-speed ports up to 1.5 V under normal operating conditions. © 2024 by the authors.
Keyword ：
electrostatic discharge (ESD) electrostatic discharge (ESD) RC trigger circuit RC trigger circuit self-biased triggered DDSCR (STDDSCR) self-biased triggered DDSCR (STDDSCR) silicon-controlled rectifier (SCR) silicon-controlled rectifier (SCR)
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| GB/T 7714 | Pan, J. , Li, F. , Wen, L. et al. A Self-Biased Triggered Dual-Direction Silicon-Controlled Rectifier Device for Low Supply Voltage Application-Specific Integrated Circuit Electrostatic Discharge Protection [J]. | Electronics (Switzerland) , 2024 , 13 (17) . |
| MLA | Pan, J. et al. "A Self-Biased Triggered Dual-Direction Silicon-Controlled Rectifier Device for Low Supply Voltage Application-Specific Integrated Circuit Electrostatic Discharge Protection" . | Electronics (Switzerland) 13 . 17 (2024) . |
| APA | Pan, J. , Li, F. , Wen, L. , Jin, J. , Huang, X. , Han, J. . A Self-Biased Triggered Dual-Direction Silicon-Controlled Rectifier Device for Low Supply Voltage Application-Specific Integrated Circuit Electrostatic Discharge Protection . | Electronics (Switzerland) , 2024 , 13 (17) . |
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This paper proposes a low-noise high-voltage rail-to-rail operational amplifier based on BCD process. For the protection of low-voltage devices in input stage, this paper proposes a common-mode voltage following circuit which not only realizes the stable performance of low-voltage input devices but also improves the gain under full supply voltage. In order to improve the response speed of large signals, this paper proposes a dynamic slew-rate enhancement technology to achieve the characteristics of low quiescent current and large slew-rate. Besides, this paper optimized the low-frequency noise of the proposed architecture. The circuit uses 180nmBCD process, and the simulation results show that after applying the above technology, the supply voltage range is 3.5-36 V, the quiescent current is about 0.99 mA, the equivalent input noise is 0.82 uVp-p, the slew-rate is 15.2 V/us, the setting time is 0.66 us and the open loop gain is 135 dB in full supply voltage range.
Keyword ：
input stage protection input stage protection operational amplifier operational amplifier slew-rate enhancement slew-rate enhancement
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| GB/T 7714 | Pan, Jie , Li, Fanyang , Yuan, Yidong et al. A Low-Noise High-Voltage Rail-to-Rail Operational Amplifier with Gain Stabilization and Slew-Rate Enhancement [J]. | 2024 27TH INTERNATIONAL SYMPOSIUM ON DESIGN & DIAGNOSTICS OF ELECTRONIC CIRCUITS & SYSTEMS, DDECS , 2024 : 41-46 . |
| MLA | Pan, Jie et al. "A Low-Noise High-Voltage Rail-to-Rail Operational Amplifier with Gain Stabilization and Slew-Rate Enhancement" . | 2024 27TH INTERNATIONAL SYMPOSIUM ON DESIGN & DIAGNOSTICS OF ELECTRONIC CIRCUITS & SYSTEMS, DDECS (2024) : 41-46 . |
| APA | Pan, Jie , Li, Fanyang , Yuan, Yidong , Zhao, Tianting , Shen, Hongwei , Wen, Liguo et al. A Low-Noise High-Voltage Rail-to-Rail Operational Amplifier with Gain Stabilization and Slew-Rate Enhancement . | 2024 27TH INTERNATIONAL SYMPOSIUM ON DESIGN & DIAGNOSTICS OF ELECTRONIC CIRCUITS & SYSTEMS, DDECS , 2024 , 41-46 . |
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Abstract ：
A direct bidirectional current discharge path between the input/output (I/O) and ground (GND) is essential for the robust protection of charging device models (CDM) in the tightly constrained design parameters of advanced low-voltage (LV) processes. Dual-direction silicon controlled rectifiers (DDSCRs) serve as ESD protection devices with high efficiency unit area discharge, enabling bidirectional electrostatic protection. However, the high trigger voltage of conventional DDSCR makes it unsuitable for ASICs used for the preamplification of biomedical signals, which only operate at low supply voltage. To address this issue, a self-biased triggered DDSCR (STDDSCR) structure is proposed to further reduce the trigger voltage. When the ESD pulse comes, the external RC trigger circuit controls the PMOS turn-on by self-bias, and the current release path is opened in advance to reduce the trigger voltage. As the ESD pulse voltage increases, the SCR loop opens to establish positive feedback and drain the amplified current. Additionally, the junction capacitance is decreased through high-resistance epitaxy and low-concentration P-well injection to further lower the trigger voltage. The simulation results of LTspice and TCAD respectively demonstrate that ESD devices can clamp transient high voltages earlier, with low parasitic capacitance and leakage current suitable for ESD protection of high-speed ports up to 1.5 V under normal operating conditions.
Keyword ：
electrostatic discharge (ESD) electrostatic discharge (ESD) RC trigger circuit RC trigger circuit self-biased triggered DDSCR (STDDSCR) self-biased triggered DDSCR (STDDSCR) silicon-controlled rectifier (SCR) silicon-controlled rectifier (SCR)
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| GB/T 7714 | Pan, Jie , Li, Fanyang , Wen, Liguo et al. A Self-Biased Triggered Dual-Direction Silicon-Controlled Rectifier Device for Low Supply Voltage Application-Specific Integrated Circuit Electrostatic Discharge Protection [J]. | ELECTRONICS , 2024 , 13 (17) . |
| MLA | Pan, Jie et al. "A Self-Biased Triggered Dual-Direction Silicon-Controlled Rectifier Device for Low Supply Voltage Application-Specific Integrated Circuit Electrostatic Discharge Protection" . | ELECTRONICS 13 . 17 (2024) . |
| APA | Pan, Jie , Li, Fanyang , Wen, Liguo , Jin, Jiazhen , Huang, Xiaolong , Han, Jiaxun . A Self-Biased Triggered Dual-Direction Silicon-Controlled Rectifier Device for Low Supply Voltage Application-Specific Integrated Circuit Electrostatic Discharge Protection . | ELECTRONICS , 2024 , 13 (17) . |
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A transient response improved digital low dropout regulator(D-LDO) is proposed in this work. With an proposed approximate constant and exponential-adaptive gain (CEAG) analog-to-frequency domain converter (AFC), the DLDO achieves improved overshoot (or undershoot) voltages with optimized settling time. In the steady state, D-LDO acts as a conventional D-LDO because of approximate constant open loop gain. While in the fine and coarse regulation state, DLDO equivalent open loop gain transfers to approximate exponential-adaptive one to improve the settling time. Simultaneously, steady state power needs not to be traded-off. Fabricated with 180nm standard CMOS process, the measurement results show that undershoot and overshoot voltages are 45mV and 25mV with load steps of 2 to 90mA (overshoot otherwise) and an edge time 40ns, respectively. The settling time and quiescent power achieve about 350ns and 63 mu W, respectively.
Keyword ：
coarse and fine tuning coarse and fine tuning digital control digital control low dropout regulator (LDO) low dropout regulator (LDO) VCO VCO
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| GB/T 7714 | Li, Fanyang , Yin, Tao , Wang, Faxiang et al. A Transient Response Improved Digital LDO with an Approximate CEAG Analog-to-Frequency Domain Converter [J]. | 2024 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, ISCAS 2024 , 2024 . |
| MLA | Li, Fanyang et al. "A Transient Response Improved Digital LDO with an Approximate CEAG Analog-to-Frequency Domain Converter" . | 2024 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, ISCAS 2024 (2024) . |
| APA | Li, Fanyang , Yin, Tao , Wang, Faxiang , Yuan, Zhanpeng . A Transient Response Improved Digital LDO with an Approximate CEAG Analog-to-Frequency Domain Converter . | 2024 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, ISCAS 2024 , 2024 . |
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This paper presents an implantable pressure sensor readout system (IPRO) which can work at low voltage and does not need internal low dropout regulator (LDO). This paper has made a series of optimizations for power consumption. The power supply part of the IPRO uses 434 MHz energy harvesting (EH), and the corresponding ultra-low power undervoltage lockout (UVLO) circuit is used. The analog front-end (AFE) and signal processing parts use current mode and differential pseudo phase locked loop (DPPLL), which can work stably under low voltage and maintain a certain degree of accuracy and power rejection ability. The wireless data transmission part adopts the impulse ultra-wide band (IR-UWB) scheme. Its ultra-low power consumption allows it to be powered by a charge pump. In order to further optimize power consumption, a simplest encoding circuit suitable for the front-end output form was proposed, and a power oscillator (PO) with accelerated starup was used to optimize area and power consumption. The system is implemented in 180 nm Complementary Metal Oxide Semiconductor (CMOS) process, with a chip area of 1.1 * 1.0 mm(2). The measurement results indicate that the typical working voltage of the IPRO is 0.8 V, the typical power consumption is 11.8 mu W, and the accuracy is 1.11 mmHg. Compared with existing designs, there is a significant optimization in supply voltage and power consumption.
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| GB/T 7714 | Li, Fanyang , Wu, Shuwen , Liu, Kaiji . A Low-Voltage and LDO-Less Wireless Pressure Sensor Readout System with Current Mode Pseudo PLL and Charge Pump Powered UWB Data Transmission for Implantable Health Monitoring [J]. | 2024 IEEE 67TH INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, MWSCAS 2024 , 2024 : 915-918 . |
| MLA | Li, Fanyang et al. "A Low-Voltage and LDO-Less Wireless Pressure Sensor Readout System with Current Mode Pseudo PLL and Charge Pump Powered UWB Data Transmission for Implantable Health Monitoring" . | 2024 IEEE 67TH INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, MWSCAS 2024 (2024) : 915-918 . |
| APA | Li, Fanyang , Wu, Shuwen , Liu, Kaiji . A Low-Voltage and LDO-Less Wireless Pressure Sensor Readout System with Current Mode Pseudo PLL and Charge Pump Powered UWB Data Transmission for Implantable Health Monitoring . | 2024 IEEE 67TH INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, MWSCAS 2024 , 2024 , 915-918 . |
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Abstract ：
This article presents an implantable pressure sensor readout system (IPRO) that can work at low voltage and does not need an internal low dropout regulator (LDO). This article has made a series of optimizations for power consumption. The power supply of IPRO uses 434-MHz energy harvesting (EH), which only uses two-stage rectification and is equipped with a corresponding ultralow power undervoltage locking (UVLO) circuit. The analog front-end (AFE) and signal-processing parts use current mode and differential pseudo-phase-locked loop (DPPLL), which can work stably under low voltage and maintain a certain degree of accuracy and power rejection ability. The wireless data transmission part adopts the impulse ultrawideband (IR-UWB) scheme. Its ultralow power consumption allows it to be powered by a charge pump, which is the first time it has been proposed in implantable systems. To further optimize power consumption, the simplest encoding circuit suitable for the front-end output form was proposed, and a power oscillator (PO) with accelerated start-up was used to optimize area and power consumption. The system is implemented in a 180-nm complementary metal oxide semiconductor (CMOS) process, with a chip area of 1.1 * 1.0 mm(2). The measurement results indicate that the typical working voltage of the IPRO is 0.8 V, the typical power consumption is 11.8 mu W, and the accuracy is 1.11 mmHg. Compared with existing designs, there is a significant optimization in supply voltage and power consumption.
Keyword ：
Charge pump Charge pump Charge pumps Charge pumps current mode current mode Data communication Data communication impulse ultrawideband (IR-UWB) impulse ultrawideband (IR-UWB) low power low power Low voltage Low voltage Monitoring Monitoring Optimization Optimization Phasor measurement units Phasor measurement units Power demand Power demand power oscillator (PO) power oscillator (PO) pseudo-PLL pseudo-PLL Sensors Sensors Wireless communication Wireless communication Wireless sensor networks Wireless sensor networks
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| GB/T 7714 | Li, Fanyang , Wu, Shuwen , Yin, Tao et al. A Low-Voltage and LDO-Less Wireless Pressure Sensor Readout System With Current Mode Pseudo-PLL and Charge Pump-Powered UWB Data Transmission for Implantable Health Monitoring [J]. | IEEE SENSORS JOURNAL , 2024 , 24 (24) : 41941-41953 . |
| MLA | Li, Fanyang et al. "A Low-Voltage and LDO-Less Wireless Pressure Sensor Readout System With Current Mode Pseudo-PLL and Charge Pump-Powered UWB Data Transmission for Implantable Health Monitoring" . | IEEE SENSORS JOURNAL 24 . 24 (2024) : 41941-41953 . |
| APA | Li, Fanyang , Wu, Shuwen , Yin, Tao , Wei, Rongshan . A Low-Voltage and LDO-Less Wireless Pressure Sensor Readout System With Current Mode Pseudo-PLL and Charge Pump-Powered UWB Data Transmission for Implantable Health Monitoring . | IEEE SENSORS JOURNAL , 2024 , 24 (24) , 41941-41953 . |
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Abstract ：
To address the power supply challenges of high performance microprocessors, a highly digitized switching LDO stmcture has been proposed, enabling LDO operation under low voltage and high load current conditions. The ripple is a significant limiting factor in the development of switching LDOs. Therefore, the proposed LDO incorporates a multi-phase pulsewidth modulation circuit (MPWM) to control the ripple within 1 mV and achieve high precision regulation and tunable active voltage positioning (AVP) function. Additionally, to further improve the transient response of the LDO and expand the range of load current, an additional analog auxiliary loop is designed. Fabricated in SMIC 55-nm CMOS, the proposed switching LDO can operate in the 0.7-1.2 V, and support a maximum load current of 1.2 A. The simulation result shows that the proposed LDO measures a maximum 61 mV overshoot with a 0.6 A load current step with 40-ns edge in high-precision mode. The measured load regulation rate is 0.4 mV/A and maximum output voltage ripple is 0.87 mV.
Keyword ：
Active voltage positioning (AVP) Active voltage positioning (AVP) Microprocessors Microprocessors pulsewidth modulation(PWM) pulsewidth modulation(PWM) switching LDO switching LDO
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| GB/T 7714 | Li, Fangyang , Deng, Wenren , Liu, Kaiji . A Highly Digital Integrated Switching LDO with Less 1 mV Output Ripple and 1.2 A Load Current [J]. | 2024 IEEE 67TH INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, MWSCAS 2024 , 2024 : 609-612 . |
| MLA | Li, Fangyang et al. "A Highly Digital Integrated Switching LDO with Less 1 mV Output Ripple and 1.2 A Load Current" . | 2024 IEEE 67TH INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, MWSCAS 2024 (2024) : 609-612 . |
| APA | Li, Fangyang , Deng, Wenren , Liu, Kaiji . A Highly Digital Integrated Switching LDO with Less 1 mV Output Ripple and 1.2 A Load Current . | 2024 IEEE 67TH INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, MWSCAS 2024 , 2024 , 609-612 . |
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In the recent audio codec standard LC3 plus, a good balance between low latency and algorithm complexity has been achieved This standard introduces a new quantization algorithm. To reduce system resource consumption and area usage, as well as to increase operation speed, this paper implements an efficient hardware architecture for the dead-zone plus uniform threshold scalar quantization (DUTSQ) algorithm under low-latency modified discrete cosine transform (LD-AMUR, based on low-latency time-domain diming cancellation (LD-TDAC) technology. The proposed quantization hardware architecture, based on state machines and folded-multiplexed data paths (SFDP) technology, significantly reduces system resource consumption. Verified using Altera MAX 10 technology, the hardware architecture operates at a frequency of 75 MHz, with logical resources occupying 16% of the total resources.
Keyword ：
Dead Zone plus Uniform Threshold Scalar Quantization (DUTSQ) Dead Zone plus Uniform Threshold Scalar Quantization (DUTSQ) LC3 plus LC3 plus Low Delay Modified Discrete Cosine Transform (LD-MDCI) Low Delay Modified Discrete Cosine Transform (LD-MDCI) state-machines and folded-multiplexed data path (SFDP) state-machines and folded-multiplexed data path (SFDP)
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| GB/T 7714 | Li, Fanyang , Yuan, Zhanpeng , Wang, Faxiang . LD-MDCT Quantization Algorithm Optimization and FPGA Realization Using DUTSQ and SFDP Techniques [J]. | 2024 IEEE THE 20TH ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS, APCCAS 2024 , 2024 : 45-49 . |
| MLA | Li, Fanyang et al. "LD-MDCT Quantization Algorithm Optimization and FPGA Realization Using DUTSQ and SFDP Techniques" . | 2024 IEEE THE 20TH ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS, APCCAS 2024 (2024) : 45-49 . |
| APA | Li, Fanyang , Yuan, Zhanpeng , Wang, Faxiang . LD-MDCT Quantization Algorithm Optimization and FPGA Realization Using DUTSQ and SFDP Techniques . | 2024 IEEE THE 20TH ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS, APCCAS 2024 , 2024 , 45-49 . |
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针对远程医疗中心电信号数据的安全传输问题，提出并设计实现了一种结合心电信号数据特征的SM4加密算法方案。该方案通过对心电信号数据的分析并结合心电信号数据的特征修改SM4加密算法结构，并使用现场可编程门阵列（FPGA）对所提出的心电信号安全传输算法进行硬件电路实现。实验结果表明，该方案在实现心电信号数据安全传输的同时也确保了加密系统能高速实时的进行数据处理。
Keyword ：
FPGA FPGA SM4加密算法 SM4加密算法 安全传输 安全传输 心电信号 心电信号
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| GB/T 7714 | 雷晓华 , 李凡阳 . 基于FPGA的心电信号加密算法研究 [J]. | 中国仪器仪表 , 2023 , 6 (04) : 37-42 . |
| MLA | 雷晓华 et al. "基于FPGA的心电信号加密算法研究" . | 中国仪器仪表 6 . 04 (2023) : 37-42 . |
| APA | 雷晓华 , 李凡阳 . 基于FPGA的心电信号加密算法研究 . | 中国仪器仪表 , 2023 , 6 (04) , 37-42 . |
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This paper presents a compact Micro-Electro-Mechanical System (MEMS) microphone digital readout system. The system is characterized by a low-dropout regulator (LDO) and a pre-amplifier and programmable-gain amplifier (PPA)-less voltage controlled oscillator (VCO)-based Delta sigma modulation technique, which improve compactness and design scalability. Specifically, to improve signal accuracy and maintain loop stability without a gain-tuning range trade-off, an active low pass filter (ALPF) and a current mode feed-forward path (CMFFP) are incorporated in a VCO-based delta-sigma modulation loop. By means of VCOs and SCG phase variation robustness and current source array feedback (CSAFB), the system achieves a high power supply rejection ratio (PSRR) and gain tuning without the need to design an extra regulator and PPA. The design was fabricated using a 180 nm Bipolar-CMOS-DMOS (BCD) process and measured at a 1.2 V supply voltage. According to the measurement results, the signal-to-noise and distortion ratio (SNDR) achieves 62 dB@1 kHz with 40 dB gain and a 10 kHz bandwidth. Furthermore, PSRR@1 kHz is below -55 dB, and power dissipation is within 57 mu W.
Keyword ：
Delta sigma modulator Delta sigma modulator microphone readout microphone readout VCO VCO
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| GB/T 7714 | Li, Fanyang , Yin, Tao , Wu, Shuwen et al. A Compact MEMS Microphone Digital Readout System Using LDO and PPA-Less VCO-Based Delta-Sigma Modulation Technique [J]. | ELECTRONICS , 2023 , 12 (24) . |
| MLA | Li, Fanyang et al. "A Compact MEMS Microphone Digital Readout System Using LDO and PPA-Less VCO-Based Delta-Sigma Modulation Technique" . | ELECTRONICS 12 . 24 (2023) . |
| APA | Li, Fanyang , Yin, Tao , Wu, Shuwen , Deng, Wenren . A Compact MEMS Microphone Digital Readout System Using LDO and PPA-Less VCO-Based Delta-Sigma Modulation Technique . | ELECTRONICS , 2023 , 12 (24) . |
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