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学者姓名：阴亚东
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Abstract ：
目的 加快中医望诊装置在社区家庭等场景中的应用普及.方法 开展了复杂背景下便携式标准化高清面舌图像采集装置研究.完成了装置的硬件设计,其尺寸为20 ×22 ×23cm3,达到了便携性要求.基于现有Mediapipe人脸特征检测算法和飞行时间(ToF)测距算法,提出了一种智能感知算法以获取使用者脸部区域的纵深、水平、垂直等3维度的位置信息;提出一种实时摄像头位移测速算法以实现其快速升降;将查找表与爬坡算法相结合,实现了一种摄像头快速自动变焦对焦算法;基于Haar级联分类器完成了一款轻量级舌体检测模型的设计;实验结果显示,在同等硬件资源下本文舌体检测模型准确率和漏检率基本与YOLOv5算法相当,但其速度提升了约23倍.结果 通过装置的语音引导和摄像头位置自适应调整,30位未经培训人员能够快速完成位姿纠正及面舌像的标准化图像采集,平均采集时间为33秒.结论 为中医望诊面舌图像采集装置的推广提供了一种新思路.
Keyword ：
Haar级联分类器 Haar级联分类器 中医面舌诊 中医面舌诊 位姿纠正 位姿纠正 图像识别 图像识别
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| GB/T 7714 | 胡真骁 , 杨朝阳 , 吴长汶 et al. 便携式复杂背景下标准化高清面舌图像采集装置研究 [J]. | 时珍国医国药 , 2024 , 35 (15) : 3493-3497 . |
| MLA | 胡真骁 et al. "便携式复杂背景下标准化高清面舌图像采集装置研究" . | 时珍国医国药 35 . 15 (2024) : 3493-3497 . |
| APA | 胡真骁 , 杨朝阳 , 吴长汶 , 伍明诚 , 王仁平 , 阴亚东 . 便携式复杂背景下标准化高清面舌图像采集装置研究 . | 时珍国医国药 , 2024 , 35 (15) , 3493-3497 . |
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本发明涉及一种间歇式频率校准OOK调制发射机电路，包括压控振荡器VCO、环路分频器、时钟发生器、鉴频器、相位差‑电压转换器和发射天线；所述鉴频器与环路分频器、时钟发生器、相位差‑电压转换器分别连接；所述压控振荡器VCO与发射天线、环路分频器、时钟发生器、相位差‑电压转换器分别连接；所述环路分频器还与时钟发生器、发射天线分别连接；所述发射机电路输入为待发射2进制数据信号DATA以及系统时钟CKs，输出为经过OOK调制后的射频信号RFO。本发明频率校准速度快，校准精度高，功耗小，可间歇性频率校准。
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| GB/T 7714 | 阴亚东 , 张泽辉 , 黄怡涛 et al. 一种间歇式频率校准OOK调制发射机电路及控制方法 : CN202210047289.7[P]. | 2022-01-17 00:00:00 . |
| MLA | 阴亚东 et al. "一种间歇式频率校准OOK调制发射机电路及控制方法" : CN202210047289.7. | 2022-01-17 00:00:00 . |
| APA | 阴亚东 , 张泽辉 , 黄怡涛 , 肖维明 , 陈志璋 . 一种间歇式频率校准OOK调制发射机电路及控制方法 : CN202210047289.7. | 2022-01-17 00:00:00 . |
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A frequency-locked loop (FLL) is proposed to provide a real-time frequency calibration for OOK power oscillator transmitters. This FLL incorporates a pulse-width detector (PWD) based on Time-Registers (TRs) to discriminate accurately between the carrier frequency and the preset target frequency during the data modulation. As a result, frequency calibration can be performed simultaneously with data modulation without interruption. A prototype of an OOK power oscillator transmitter integrated with the proposed FLL is implemented with onboard discrete electronic elements for demonstration. The measurement indicates that the FLL can accurately lock to a carrier frequency of 160MHz despite electromagnetic (EM) interference in the loop antenna of the transmitter. In contrast, with EM interference and charge leakage, the carrier frequency differs from the expected value by about 1 MHz when the FLL is disabled.
Keyword ：
Frequency-locked loop (FLL) Frequency-locked loop (FLL) OOK modulation OOK modulation power oscillator transmitter power oscillator transmitter pulse-width detection pulse-width detection time register time register
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| GB/T 7714 | Yin, Yadong , Zhang, Zehui , Xiao, Weiming et al. An FLL Providing Real-Time Frequency Calibration for OOK Power Oscillator Transmitters [J]. | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS , 2023 , 70 (9) : 3233-3237 . |
| MLA | Yin, Yadong et al. "An FLL Providing Real-Time Frequency Calibration for OOK Power Oscillator Transmitters" . | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS 70 . 9 (2023) : 3233-3237 . |
| APA | Yin, Yadong , Zhang, Zehui , Xiao, Weiming , Fu, Ximing , El-Sankary, Kamal , Pun, Sio-Hang . An FLL Providing Real-Time Frequency Calibration for OOK Power Oscillator Transmitters . | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS , 2023 , 70 (9) , 3233-3237 . |
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An integrated lock-in amplifier (LIA) with automatic phase tuning and second-order harmonic frequency extraction is presented in this paper. The automatic phase alignment loop implemented in the proposed single-channel LIA can directly align the phases of an input signal with a reference signal. Furthermore, the proposed LIA system also includes an enhanced signal detection method in which the 2(nd) harmonics of the carrier frequency (omega(ref)) is applied. As opposed to conventional LIA, this method reduces flicker noise and input offset effects that limit the signal-to-noise ratio (SNR). In terms of signal power detection, the proposed single-channel LIA architecture does not require phase synchronization between input and reference signals. The circuit is designed for a reference frequency of 100 Hz, suitable for biomedical applications. The LIA is Implemented using 0.18-mu m CMOS technology with a single power supply voltage of 1.8 V. The system consumes 360 mu W at an operating frequency of 100 Hz and presents a high input sensitivity dynamic range for a detection bandwidth of 50 Hz and a FOM of 116 dB.
Keyword ：
automatic phase tuning automatic phase tuning finite-state machine finite-state machine flicker noise flicker noise Lock-in amplifier Lock-in amplifier SAR SAR semi-digital semi-digital switch capacitor integrator switch capacitor integrator
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| GB/T 7714 | Fu, Ximing , Colombo, Dalton Martini , Alamdari, Hamed Hanafi et al. Lock-In Amplifier for Sensor Application Using Second Order Harmonic Frequency With Automatic Background Phase Calibration [J]. | IEEE SENSORS JOURNAL , 2022 , 22 (16) : 16067-16080 . |
| MLA | Fu, Ximing et al. "Lock-In Amplifier for Sensor Application Using Second Order Harmonic Frequency With Automatic Background Phase Calibration" . | IEEE SENSORS JOURNAL 22 . 16 (2022) : 16067-16080 . |
| APA | Fu, Ximing , Colombo, Dalton Martini , Alamdari, Hamed Hanafi , Yin, Yadong , El-Sankary, Kamal . Lock-In Amplifier for Sensor Application Using Second Order Harmonic Frequency With Automatic Background Phase Calibration . | IEEE SENSORS JOURNAL , 2022 , 22 (16) , 16067-16080 . |
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In this brief, a blind background calibration technique for super-regenerative receivers (SRRs) is presented. The proposed calibration scheme is designed to help SRRs to maintain their high sensitivity and immunity to negative transconductance (-G(m)) variations under process-voltage- temperature (PVT) variations. Unlike the conventional foreground -G(m) variations calibration techniques that require interruption of the receiver input, the proposed calibration technique employs input signal statistics and does not require interruption of the input bit-stream for extraction of the errors. The proposed scheme is based on an adaptive algorithm that compares the probability distribution of the pseudorandom-input (PI) stream and the output of the super-regenerative oscillator (SRO) and forces them to coincide at the end of the calibration. The proposed technique is implemented using a mixed-signal detection circuit and a finite state machine (FSM) that drives an 8-bit successive approximation register (SAR) to adjust the compensation current in the SRO. The simulation results successfully verify the effectiveness and reliability of the proposed calibration technique and show significant improvements in terms of SRR sensitivity under different process corners.
Keyword ：
blind calibration blind calibration current steering DAC current steering DAC envelope detector envelope detector offset cancelation offset cancelation PVT variations PVT variations Super-regenerative receiver Super-regenerative receiver system offset system offset
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| GB/T 7714 | Fu, Ximing , El-Sankary, Kamal , Ge, Yang et al. A Blind Background Calibration Technique for Super-Regenerative Receivers [J]. | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS , 2022 , 69 (2) : 344-348 . |
| MLA | Fu, Ximing et al. "A Blind Background Calibration Technique for Super-Regenerative Receivers" . | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS 69 . 2 (2022) : 344-348 . |
| APA | Fu, Ximing , El-Sankary, Kamal , Ge, Yang , Yin, Yadong , Truhachev, Dmitri . A Blind Background Calibration Technique for Super-Regenerative Receivers . | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS , 2022 , 69 (2) , 344-348 . |
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The conventional phase-locked loops or frequency-locked loops should take time to calibrate the oscillator's resonant frequency in a super-regenerative receiver (SRR) and severely disrupts the receiver's operations. This paper proposes a novel intermittent frequency locked loop (IFLL) as a frequency synthesizer to continuously maintain the resonant frequency equal to the preset target frequency without interruption to the SRR. An analog loop mainly composed of a time-register-based frequency detector and a charge pump is proposed to achieve precise frequency detection during each SRR's quenching period regardless of the inevitable initial phase error, and adjust SRR's resonant frequency accordingly. An average fractional division scheme is adopted to improve IFLL's frequency resolution to the level of the quenching frequency. The operations of the IFLL are analyzed with the z-domain transfer function, including the stability and frequency response. A prototype is built and tested. The measurement results show that the proposed IFLL only needs a calibration cycle of fewer than 50 its to adjust SRR's resonant frequency without interruption against its receiving. The real-time frequency error after calibration is smaller than 70 kHz. SRR opposes a sensitivity of -61.2 dBm @ 200 kbps and a 3-dB bandwidth of 2.2 MHz.
Keyword ：
Average fractional division scheme Average fractional division scheme background frequency calibration background frequency calibration frequency-locked loop frequency-locked loop initial phase error initial phase error phase-locked loop phase-locked loop super-regenerative receiver super-regenerative receiver time register time register
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| GB/T 7714 | Yin, Yadong , Huang, Yitao , Chen, Zhizhang et al. A Fast Background Frequency Calibration Based on Intermittent Frequency Locked Loop for the Super-Regenerative Receive [J]. | IEEE ACCESS , 2022 , 10 : 115624-115634 . |
| MLA | Yin, Yadong et al. "A Fast Background Frequency Calibration Based on Intermittent Frequency Locked Loop for the Super-Regenerative Receive" . | IEEE ACCESS 10 (2022) : 115624-115634 . |
| APA | Yin, Yadong , Huang, Yitao , Chen, Zhizhang , Pun, Sio-Hang , Liao, Yipeng , Gao, Yueming et al. A Fast Background Frequency Calibration Based on Intermittent Frequency Locked Loop for the Super-Regenerative Receive . | IEEE ACCESS , 2022 , 10 , 115624-115634 . |
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This article proposes and implements a sampling-clockless quasi-digital frequency-key-shifting (FSK) demodulator with a strong tolerance against carrier-frequency offset. To precisely discriminate periods of the FSK signal without a high-frequency sampling clock, quasi-digital time registers are used to construct pulse-width comparators (PWC) to demodulate the FSK signal, which are robust against the process, voltage, and temperature variation. In addition, a discrete-time differentiator is proposed and integrated into the demodulator to efficiently reject the inevitable carrier frequency offset and drift of the FSK signal. The demodulator is prototyped, analyzed, implemented, and tested. The measurement results show that the demodulator can demodulate FSK signal with a data rate of 1 Mbps and a modulation index of 0.5, while only requiring a 10.7 dB signal-to-noise ratio to achieve a demodulation quality with a bit-error ratio of no more than 10-3 while tolerating a frequency offset or drift in the range of -0.56 to 0.48 MHz. © 2022, Science Press. All right reserved.
Keyword ：
Clocks Clocks Comparator circuits Comparator circuits Comparators (optical) Comparators (optical) Demodulation Demodulation Demodulators Demodulators Frequency shift keying Frequency shift keying Optical variables measurement Optical variables measurement Signal to noise ratio Signal to noise ratio
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| GB/T 7714 | Yin, Yadong , Huang, Yitao . Sampling-clockless quasi-digital FSK demodulator implemented with time-register-based pulse-width comparators and a discrete-time differentiator [J]. | Chinese Journal of Scientific Instrument , 2022 , 43 (8) : 147-153 . |
| MLA | Yin, Yadong et al. "Sampling-clockless quasi-digital FSK demodulator implemented with time-register-based pulse-width comparators and a discrete-time differentiator" . | Chinese Journal of Scientific Instrument 43 . 8 (2022) : 147-153 . |
| APA | Yin, Yadong , Huang, Yitao . Sampling-clockless quasi-digital FSK demodulator implemented with time-register-based pulse-width comparators and a discrete-time differentiator . | Chinese Journal of Scientific Instrument , 2022 , 43 (8) , 147-153 . |
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为了满足便携式电子产品的需求,设计了一种电流叠加型无损电流检测器和基于该检测器的升压型变换器.该电流检测器采用并联于电感两端的RC网络将电感电流转换成电压信号而实现电流的无损检测,利用电压-电流转换电路将检测电压和斜坡补偿电压转换为电流进行叠加并转换成电压作为最终检测结果.与现有电流检测器相比,该电流检测器具有结构简单、功率损耗小、精度高、响应速度快等优点.基于SMIC 0.18μm CMOS工艺完成了整体电路设计和版图参数提取后仿真验证.后仿真结果显示,当电感电流在0～600 mA范围内变化时,电流检测器检测误差小于2.9％,功耗仅为0.05 mW;当输入电压为3 V时,在100 mA输出电流下变换器转换效率可达92％,负载调整率和线性调整率分别为0.51％和0.23％.
Keyword ：
升压型变换器 升压型变换器 斜坡补偿技术 斜坡补偿技术 无损电流检测 无损电流检测 电流叠加技术 电流叠加技术
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| GB/T 7714 | 许亦云 , 张利红 , 阴亚东 . 一种基于电流叠加型无损电流检测的升压型变换器 [J]. | 电子元件与材料 , 2022 , 41 (10) : 1072-1077 . |
| MLA | 许亦云 et al. "一种基于电流叠加型无损电流检测的升压型变换器" . | 电子元件与材料 41 . 10 (2022) : 1072-1077 . |
| APA | 许亦云 , 张利红 , 阴亚东 . 一种基于电流叠加型无损电流检测的升压型变换器 . | 电子元件与材料 , 2022 , 41 (10) , 1072-1077 . |
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提出了一种适用于反向降压(InvBuck)型负压直流-直流(DC-DC)变换器的功率管驱动电路.该驱动电路将输入的脉宽调制(PWM)信号生成两路非重叠的正压驱动信号,然后利用负压DC-DC变换器中飞电容的电压反转产生负压驱动信号.该驱动电路中所有MOS管以及功率管的漏源电压(VDS)均不超过输入电源电压(≤VIN),因而可用标准CMOS工艺实现.采用SMIC 0.18μm标准CMOS工艺完成了电路设计和仿真验证.结果表明,在900 kHz开关频率和5 V电源电压下,当PWM信号占空比在20％～90％范围变化时,本电路联合驱动功率管产生-0.99～-4.47 V的输出电压,仿真结果与理论计算值误差不超过0.7％,在输出最大电流100 mA时转换效率均大于91％.
Keyword ：
功率管驱动 功率管驱动 反向降压型变换器 反向降压型变换器 负压 负压 非重叠 非重叠 飞电容 飞电容
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| GB/T 7714 | 苏东来 , 韦孟宇 , 高跃明 et al. 负压DC-DC变换器中新型功率管驱动电路 [J]. | 电子元件与材料 , 2022 , 41 (12) : 1351-1356 . |
| MLA | 苏东来 et al. "负压DC-DC变换器中新型功率管驱动电路" . | 电子元件与材料 41 . 12 (2022) : 1351-1356 . |
| APA | 苏东来 , 韦孟宇 , 高跃明 , 阴亚东 . 负压DC-DC变换器中新型功率管驱动电路 . | 电子元件与材料 , 2022 , 41 (12) , 1351-1356 . |
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A Bandgap reference (BGR) circuit with a new high-order curvature-compensation technique is proposed in this paper. The curvature method operates by adding up two correction voltages. The first one is proportional to the difference in gate-source voltages of two MOS transistors (Delta V-GS) operating in weak inversion mode, while the second one (V-NL) is generated using a nonlinear current created by a piecewise-linear circuit. To improve the power supply rejection ratio (PSRR) and the line regulation performance, a low-power pre-regulator isolates the circuit power supply and BGR output. Additionally, the chopping technique reduces the output voltage noise and offset. Consequently, the overall PVT robustness of the proposed circuit is significantly improved. The circuit was implemented using a thick-oxide transistor in a standard 0.18 mu m CMOS technology with a 3.3 V power supply voltage. The silicon results exhibit a temperature coefficient of 5-15 ppm/degrees C in the temperature range of -10 degrees C to 110 degrees C, whereas the simulated results demonstrate a similar performance within the temperature range of -40 degrees C to 150 degrees C. The supply current consumption is 150 mu A, and the chip area is 0.56 x 0.8 mm(2). The measured peak noise at the output is 1.42 mu V/root Hz @320 Hz, the measured PSRR @ 1 kHz is -80 dB, and the line regulation performance is 10 ppm/V, making the proposed circuit suitable for applications requiring low noise, high-order temperature compensation, and robust PVT performance.
Keyword ：
BGR BGR curvature compensation curvature compensation low area low area low-power operation low-power operation Pre-regulator Pre-regulator subthreshold subthreshold temperature coefficient temperature coefficient
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| GB/T 7714 | Fu, Ximing , Colombo, Dalton Martini , Yin, Yadong et al. Low Noise, High PSRR, High-Order Piecewise Curvature Compensated CMOS Bandgap Reference [J]. | IEEE ACCESS , 2022 , 10 : 110970-110982 . |
| MLA | Fu, Ximing et al. "Low Noise, High PSRR, High-Order Piecewise Curvature Compensated CMOS Bandgap Reference" . | IEEE ACCESS 10 (2022) : 110970-110982 . |
| APA | Fu, Ximing , Colombo, Dalton Martini , Yin, Yadong , El-Sankary, Kamal . Low Noise, High PSRR, High-Order Piecewise Curvature Compensated CMOS Bandgap Reference . | IEEE ACCESS , 2022 , 10 , 110970-110982 . |
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