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学者姓名：黄世震
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Abstract ：
Graph convolution networks (GCN) have demonstrated success in learning graph structures; however, they are limited in inductive tasks. Graph attention networks (GAT) were proposed to address the limitations of GCN and have shown high performance in graph -based tasks. Despite this success, GAT faces challenges in hardware acceleration, including: 1) The GAT algorithm has difficulty adapting to hardware; 2) challenges in efficiently implementing Sparse matrix multiplication (SPMM); and 3) complex addressing and pipeline stall issues due to irregular memory accesses. To this end, this paper proposed SH-GAT, an FPGA-based GAT accelerator that achieves more efficient GAT inference. The proposed approach employed several optimizations to enhance GAT performance. First, this work optimized the GAT algorithm using split weights and softmax approximation to make it more hardware -friendly. Second, a load -balanced SPMM kernel was designed to fully leverage potential parallelism and improve data throughput. Lastly, data preprocessing was performed by pre -fetching the source node and its neighbor nodes, effectively addressing pipeline stall and complexly addressing issues arising from irregular memory access. SH-GAT was evaluated on the Xilinx FPGA Alveo U280 accelerator card with three popular datasets. Compared to existing CPU, GPU, and state-of-the-art (SOTA) FPGA-based accelerators, SH-GAT can achieve speedup by up to 3283x, 13x, and 2.3x.
Keyword ：
accelerator accelerator co-design co-design FPGA FPGA graph graph graph attention networks graph attention networks
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| GB/T 7714 | Wang, Renping , Li, Shun , Tang, Enhao et al. SH-GAT: Software-hardware co-design for accelerating graph attention networks on FPGA [J]. | ELECTRONIC RESEARCH ARCHIVE , 2024 , 32 (4) : 2310-2322 . |
| MLA | Wang, Renping et al. "SH-GAT: Software-hardware co-design for accelerating graph attention networks on FPGA" . | ELECTRONIC RESEARCH ARCHIVE 32 . 4 (2024) : 2310-2322 . |
| APA | Wang, Renping , Li, Shun , Tang, Enhao , Lan, Sen , Liu, Yajing , Yang, Jing et al. SH-GAT: Software-hardware co-design for accelerating graph attention networks on FPGA . | ELECTRONIC RESEARCH ARCHIVE , 2024 , 32 (4) , 2310-2322 . |
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G protein-coupled receptors (GPCRs) have been the targets for more than 40% of the currently approved drugs. Although neural networks can effectively improve the accuracy of prediction with the biological activity, the result is undesirable in the limited orphan GPCRs (oGPCRs) datasets. To this end, we proposed Multi-source Transfer Learning with Graph Neural Network, called MSTL-GNN, to bridge this gap. Firstly, there are three ideal sources of data for transfer learning, oGPCRs, experimentally validated GPCRs, and invalidated GPCRs similar to the former one. Secondly, the SIMLEs format GPCRs convert to graphics, and they can be the input of Graph Neural Network (GNN) and ensemble learning for improving prediction accuracy. Finally, our experiments show that MSTL-GNN remarkably improves the prediction of GPCRs ligand activity value compared with previous studies. On average, the two evaluation indexes we adopted, R2 and Root-mean-square deviation (RMSE). Compared with the state-of-the-art work MSTL-GNN increased up to 67.13% and 17.22%, respectively. The effectiveness of MSTL-GNN in the field of GPCR Drug discovery with limited data also paves the way for other similar application scenarios.
Keyword ：
biological activity biological activity G protein-coupled receptors (GPCRs) G protein-coupled receptors (GPCRs) Graph Neural Network Graph Neural Network multi-source transfer learning multi-source transfer learning
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| GB/T 7714 | Huang, Shizhen , Zheng, ShaoDong , Chen, Ruiqi . Multi-source transfer learning with Graph Neural Network for excellent modelling the bioactivities of ligands targeting orphan G protein-coupled receptors [J]. | MATHEMATICAL BIOSCIENCES AND ENGINEERING , 2023 , 20 (2) : 2588-2608 . |
| MLA | Huang, Shizhen et al. "Multi-source transfer learning with Graph Neural Network for excellent modelling the bioactivities of ligands targeting orphan G protein-coupled receptors" . | MATHEMATICAL BIOSCIENCES AND ENGINEERING 20 . 2 (2023) : 2588-2608 . |
| APA | Huang, Shizhen , Zheng, ShaoDong , Chen, Ruiqi . Multi-source transfer learning with Graph Neural Network for excellent modelling the bioactivities of ligands targeting orphan G protein-coupled receptors . | MATHEMATICAL BIOSCIENCES AND ENGINEERING , 2023 , 20 (2) , 2588-2608 . |
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Automatic License Plate Recognition (ALPR) systems have become popular application areas of the Internet of Things (IoT). A typical ALPR system always needs powerful processors such as Cortex-A7. However, most known system for Standard Definition (SD) are not suitable for real-time High Definition (HD) image processing and low power consuming requirement in IoT. A HD ALPR accelerator for the IoT endpoint System on Chip (SoC) is proposed in this paper to meet the needs of computations. Based on the programming flexibility of IoT endpoint SoC, it can switch between HD and SD resolutions, which can avoid the specific resolution switching algorithm. A Field Programmable Gate Array (FPGA) chip is transplanted the Cortex-M0 as the IoT endpoint SoC, through the design of ALPR accelerator and Cortex-M0, data communication is achieved by First-In, First-Out (FIFO) with AMBA High-performance Bus (AHB) interface. Heterogeneous implementation of ALPR system has shown that this HD ALPR algorithm can recognize a license plate in 12.5ms, with a success rate of 95.5%. The system utilizes 41,763 Look-Up-Tables (LUTs) without special FPGA IP core. The comparison shows that the system proposed in this paper makes performance of the SoC based on the Cortex-M0 kernel was two times higher than the Cortex-A72 SoC and 39% of the power consumption of Zynq-7000 that is typical heterogeneous ALPR platform. © The Author('s). This is an open access article distributed under the terms of the Creative Commons Attribution License (CC BY 4.0), which permits unrestricted use, distribution, and reproduction in any medium, provided the original author and source are cited.
Keyword ：
Application specific integrated circuits Application specific integrated circuits Automatic vehicle identification Automatic vehicle identification Digital television Digital television Field programmable gate arrays (FPGA) Field programmable gate arrays (FPGA) Image processing Image processing Internet of things Internet of things License plates (automobile) License plates (automobile) Optical character recognition Optical character recognition Programmable logic controllers Programmable logic controllers System-on-chip System-on-chip Table lookup Table lookup
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| GB/T 7714 | Huang, Shizhen , Lin, Mengru , Yu, Fan et al. Real-time high definition license plate localization and recognition accelerator for IoT endpoint system on chip [J]. | Journal of Applied Science and Engineering (Taiwan) , 2022 , 25 (1) : 1-11 . |
| MLA | Huang, Shizhen et al. "Real-time high definition license plate localization and recognition accelerator for IoT endpoint system on chip" . | Journal of Applied Science and Engineering (Taiwan) 25 . 1 (2022) : 1-11 . |
| APA | Huang, Shizhen , Lin, Mengru , Yu, Fan , Chen, Ruiqi , Zhang, Lei , Zhu, Yanxiang . Real-time high definition license plate localization and recognition accelerator for IoT endpoint system on chip . | Journal of Applied Science and Engineering (Taiwan) , 2022 , 25 (1) , 1-11 . |
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The transformer model has recently been a milestone in artificial intelligence. The algorithm has enhanced the performance of tasks such as Machine Translation and Computer Vision to a level previously unattainable. However, the transformer model has a strong performance but also requires a high amount of memory overhead and enormous computing power. This significantly hinders the deployment of an energy-efficient transformer system. Due to the high parallelism, low latency, and low power consumption of field-programmable gate arrays (FPGAs) and application specific integrated circuits (ASICs), they demonstrate higher energy efficiency than Graphics Processing Units (GPUs) and Central Processing Units (CPUs). Therefore, FPGA and ASIC are widely used to accelerate deep learning algorithms. Several papers have addressed the issue of deploying the Transformer on dedicated hardware for acceleration, but there is a lack of comprehensive studies in this area. Therefore, we summarize the transformer model compression algorithm based on the hardware accelerator and its implementation to provide a comprehensive overview of this research domain. This paper first introduces the transformer model framework and computation process. Secondly, a discussion of hardware-friendly compression algorithms based on self-attention and Transformer is provided, along with a review of a state-of-the-art hardware accelerator framework. Finally, we considered some promising topics in transformer hardware acceleration, such as a high-level design framework and selecting the optimum device using reinforcement learning.
Keyword ：
compression compression FPGA FPGA hardware accelerators hardware accelerators self-attention self-attention transformer transformer
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| GB/T 7714 | Huang, Shizhen , Tang, Enhao , Li, Shun et al. Hardware-friendly compression and hardware acceleration for transformer: A survey [J]. | ELECTRONIC RESEARCH ARCHIVE , 2022 , 30 (10) : 3755-3785 . |
| MLA | Huang, Shizhen et al. "Hardware-friendly compression and hardware acceleration for transformer: A survey" . | ELECTRONIC RESEARCH ARCHIVE 30 . 10 (2022) : 3755-3785 . |
| APA | Huang, Shizhen , Tang, Enhao , Li, Shun , Ping, Xiangzhan , Chen, Ruiqi . Hardware-friendly compression and hardware acceleration for transformer: A survey . | ELECTRONIC RESEARCH ARCHIVE , 2022 , 30 (10) , 3755-3785 . |
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With the recent developments in the internet of things (IoT), there has been a significant rapid generation of data. Theoretically, machine learning can help edge devices by providing a better analysis and processing of data near the data source. However, solving the nonlinear optimisation problem is time-consuming for IoT edge devices. A standard method for solving the nonlinear optimisation problems in machine learning models is the Broyden-Fletcher-Goldfarb-Shanno (BFGS-QN) method. Since the field-programmable gate arrays (FPGAs) are customisable, reconfigurable, highly parallel and cost-effective, the present study envisaged the implementation of the BFGS-QN algorithm on an FPGA platform. The use of half-precision floating-point numbers and single-precision floating-point numbers to save the FPGA resources were adopted to implement the BFGS-QN algorithm on an FPGA platform. The results indicate that compared to the single-precision floating-point numbers, the implementation of the mixed-precision BFGS-QN algorithm reduced 27.1% look-up tables, 18.2% flip-flops and 17.9% distributed random memory. Copyright © 2022 Inderscience Enterprises Ltd.
Keyword ：
Cost effectiveness Cost effectiveness Digital arithmetic Digital arithmetic Edge computing Edge computing Field programmable gate arrays (FPGA) Field programmable gate arrays (FPGA) Flip flop circuits Flip flop circuits Fluorine compounds Fluorine compounds Internet of things Internet of things Learning systems Learning systems Logic gates Logic gates Machine learning Machine learning Nonlinear programming Nonlinear programming Table lookup Table lookup
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| GB/T 7714 | Huang, Shizhen , Guo, Anhua , Su, Kaikai et al. Implementation of quasi-Newton algorithm on FPGA for IoT endpoint devices [J]. | International Journal of Security and Networks , 2022 , 17 (2) : 124-134 . |
| MLA | Huang, Shizhen et al. "Implementation of quasi-Newton algorithm on FPGA for IoT endpoint devices" . | International Journal of Security and Networks 17 . 2 (2022) : 124-134 . |
| APA | Huang, Shizhen , Guo, Anhua , Su, Kaikai , Chen, Siyu , Chen, Ruiqi . Implementation of quasi-Newton algorithm on FPGA for IoT endpoint devices . | International Journal of Security and Networks , 2022 , 17 (2) , 124-134 . |
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In the drug discovery process, the biological activity value (BAV) of G Protein-Coupled Receptors (GPCRs) targeting ligands is a large consideration. Past BAV prediction on CPU consumes tremendous time and power, yet there is rarely any related acceleration research. Therefore, this paper proposes a series of heterogeneous FPGA-based accelerators for well-performing algorithms to predict GPCRs ligands BAV. Communication delay is reduced by compressing the sparse matrix and directly coupling accelerators on the system BUS. Computation is accelerated by the remapping during the weight storage. Experimental results show that our FPGA accelerator implemented on Xilinx XCZU7EV performs 54:5x faster than CPU and 35:2x more energy-efficient than GPU.
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| GB/T 7714 | Chen, Ruiqi , Ma, Yuhanxiao , Zheng, Shaodong et al. Biological Activity Prediction of GPCR-targeting Ligands on Heterogeneous FPGA-based Accelerators [J]. | 2022 IEEE 30TH INTERNATIONAL SYMPOSIUM ON FIELD-PROGRAMMABLE CUSTOM COMPUTING MACHINES (FCCM 2022) , 2022 : 237-237 . |
| MLA | Chen, Ruiqi et al. "Biological Activity Prediction of GPCR-targeting Ligands on Heterogeneous FPGA-based Accelerators" . | 2022 IEEE 30TH INTERNATIONAL SYMPOSIUM ON FIELD-PROGRAMMABLE CUSTOM COMPUTING MACHINES (FCCM 2022) (2022) : 237-237 . |
| APA | Chen, Ruiqi , Ma, Yuhanxiao , Zheng, Shaodong , Huang, Shizhen , Chen, Chao , Yu, Jun et al. Biological Activity Prediction of GPCR-targeting Ligands on Heterogeneous FPGA-based Accelerators . | 2022 IEEE 30TH INTERNATIONAL SYMPOSIUM ON FIELD-PROGRAMMABLE CUSTOM COMPUTING MACHINES (FCCM 2022) , 2022 , 237-237 . |
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Covid-19 has been threatening human life and is now the most serious public health issue in the world. During this pandemic, wearing masks is one of the most effective ways to inhibit virus transmission. However, existing ubiquitous identity recognition requires people to remove their masks to complete facial recognition, which is highly risky. Iris recognition, as a safer applicable identification method, has its fatal weakness of not being able to achieve satisfactory real-time recognition on end devices. This paper presents an edge deployment of a low-power iris recognition system based on FPGA with approximate multipliers. We adopted a serial-parallel hybrid method for the preprocessing stage, trained the CNN model on PC and then deployed the architecture and parameters on FPGA. We further reduced power and resource consumption by designing approximate multipliers for the key calculation. Experimental results show that design achieves up 28% and 43% gain in terms of area and latency energy product, while incurring a negligible accuracy loss. The recognition speed increased by 40% compared with Raspberry Pi, 11 times better than Jetson Nano power latency production. © 2021 Computer Society of the Republic of China. All rights reserved.
Keyword ：
Biometrics Biometrics Face recognition Face recognition Field programmable gate arrays (FPGA) Field programmable gate arrays (FPGA) Integrated circuit design Integrated circuit design
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| GB/T 7714 | Lin, Meng-Ru , Huang, Shi-Zhen , Li, Fu-Shan et al. Low-power Iris Recognition System Implementation on FPGA with Approximate Multiplier [J]. | Journal of Computers (Taiwan) , 2021 , 32 (5) : 115-127 . |
| MLA | Lin, Meng-Ru et al. "Low-power Iris Recognition System Implementation on FPGA with Approximate Multiplier" . | Journal of Computers (Taiwan) 32 . 5 (2021) : 115-127 . |
| APA | Lin, Meng-Ru , Huang, Shi-Zhen , Li, Fu-Shan , Chen, Rui-Qi , Tang, Shi-Di . Low-power Iris Recognition System Implementation on FPGA with Approximate Multiplier . | Journal of Computers (Taiwan) , 2021 , 32 (5) , 115-127 . |
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为了能充分利用冗余信息,以提高定位精度与实用性,本文提出了一种基于Levenberg-Markuardt(LM)算法的可见光室内定位方法.该方法主要通过将非线性奇异方程组转化为无约束最优化函数,再利用信赖域技巧修正的LM算法获得全局收敛解.本文针对LED灯进行辐射分析,提出了对应的信道模型,同时,还探究了算法在非负参数μ的不同表达式下的性能表现.结果表明,该模型与广义朗伯模型具有一致性,且非负参数μ选取合适时算法最少只需17次迭代,而基于此的定位系统在1.48 m×1.51 m×1.65 m场景下的定位误差为12.4 cm左右.
Keyword ：
LED辐射模型 LED辐射模型 LM算法 LM算法 信赖域 信赖域 可见光 可见光 室内定位 室内定位 最优化 最优化
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| GB/T 7714 | 潘富圣 , 黄世震 . 基于改进LM算法的可见光定位研究 [J]. | 电子产品世界 , 2020 , 27 (11) : 75-78 . |
| MLA | 潘富圣 et al. "基于改进LM算法的可见光定位研究" . | 电子产品世界 27 . 11 (2020) : 75-78 . |
| APA | 潘富圣 , 黄世震 . 基于改进LM算法的可见光定位研究 . | 电子产品世界 , 2020 , 27 (11) , 75-78 . |
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Gesture recognition is critical in the field of Human-Computer Interaction, especially in healthcare, rehabilitation, sign language translation, etc. Conventionally, the gesture recognition data collected by the inertial measurement unit (IMU) sensors is relayed to the cloud or a remote device with higher computing power to train models. However, it is not convenient for remote follow-up treatment of movement rehabilitation training. In this paper, based on a field-programmable gate array (FPGA) accelerator and the Cortex-M0 IP core, we propose a wearable deep learning system that is capable of locally processing data on the end device. With a pre-stage processing module and serial-parallel hybrid method, the device is of low-power and low-latency at the micro control unit (MCU) level, however, it meets or exceeds the performance of single board computers (SBC). For example, its performance is more than twice as much of Cortex-A53 (which is usually used in Raspberry Pi). Moreover, a convolutional neural network (CNN) and a multilayer perceptron neural network (NN) is used in the recognition model to extract features and classify gestures, which helps achieve a high recognition accuracy at 97%. Finally, this paper offers a software-hardware co-design method that is worth referencing for the design of edge devices in other scenarios.
Keyword ：
accelerator, inertial measurement unit (IMU) accelerator, inertial measurement unit (IMU) field-programmable gate array (FPGA) field-programmable gate array (FPGA) gesture recognition, convolutional neural network (CNN) gesture recognition, convolutional neural network (CNN) micro-control unit (MCU) micro-control unit (MCU)
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| GB/T 7714 | Jiang, Weibin , Ye, Xuelin , Chen, Ruiqi et al. Wearable on-device deep learning system for hand gesture recognition based on FPGA accelerator [J]. | MATHEMATICAL BIOSCIENCES AND ENGINEERING , 2020 , 18 (1) : 132-153 . |
| MLA | Jiang, Weibin et al. "Wearable on-device deep learning system for hand gesture recognition based on FPGA accelerator" . | MATHEMATICAL BIOSCIENCES AND ENGINEERING 18 . 1 (2020) : 132-153 . |
| APA | Jiang, Weibin , Ye, Xuelin , Chen, Ruiqi , Su, Feng , Lin, Mengru , Ma, Yuhanxiao et al. Wearable on-device deep learning system for hand gesture recognition based on FPGA accelerator . | MATHEMATICAL BIOSCIENCES AND ENGINEERING , 2020 , 18 (1) , 132-153 . |
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In this paper, a design method of an infusion monitoring device using a 5kg load cell was proposed, and a material object with a monitoring accuracy of 0.1g was fabricated by this method. Usually, the use of load cells to monitor the infusion situation will face a variety of external disturbances. This paper ensured that the correct data was filtered out via the range analysis of the measured values and software filtering, and summed up all kinds of errors that may occur, which made the device have the ability to judge varieties of errors. Besides, the selection of different thresholds in the range was explored so that the device can dynamically adjust the threshold according to different drug solutions, different rate requirements, and different infusion sets. Furthermore, this paper proposed the equation and method of temperature correction. The results show that the proposed design method made the device more practical. © 2019 IEEE.
Keyword ：
Computers Computers Computer science Computer science Design Design Engineering Engineering Industrial engineering Industrial engineering
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| GB/T 7714 | Huang, Shizhen , Pan, Fusheng . Design of robust intravenous infusion monitoring device [C] . 2019 : 1949-1952 . |
| MLA | Huang, Shizhen et al. "Design of robust intravenous infusion monitoring device" . (2019) : 1949-1952 . |
| APA | Huang, Shizhen , Pan, Fusheng . Design of robust intravenous infusion monitoring device . (2019) : 1949-1952 . |
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