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学者姓名：朱文兴
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. Non-convex optimization regularized with a sparsity function has many applications in machine learning and other fields. Non-convex relaxation of the sparsity function often leads to more effective sparse optimization algorithms. In this paper, we propose a new weighted regularizer to approximate the sparsity function, and derive a weighted thresholding operator for the sparse optimization problem with the regularizer. Then, iterative weighted thresholding algorithms are designed, followed with an acceleration by using Nesterov's acceleration method and non-monotone line search. Under the Kurdyka- Lojasiewicz (KL) property, the smoothness and the appropriate convexity assumptions, we prove that the two algorithms are convergent and the convergence rates are O(1/k) and O(1/k2) respectively, where k is the iteration counter. Moreover, we develop convergent practical homotopy algorithms by invoking the two iterative weighted thresholding algorithms as subroutines respectively. A series of numerical experiments demonstrate that our algorithms are superior in both average recovery rate and average running time for the sparse recovery problem, and are competitive in solution quality and average running time for the logistic regression problem, compared to state-of-the-art algorithms.
Keyword ：
homotopy technique homotopy technique iterative weighted thresholding algorithm iterative weighted thresholding algorithm sparse solution sparse solution weighted regularizer weighted regularizer
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| GB/T 7714 | Huang, Zilin , Jiang, Lanfan , Cao, Weiwei et al. NONCONVEX REGULARIZER AND HOMOTOPY-BASED SPARSE OPTIMIZATION: CONVERGENT ALGORITHMS AND APPLICATIONS [J]. | JOURNAL OF INDUSTRIAL AND MANAGEMENT OPTIMIZATION , 2025 , 21 (5) : 3541-3579 . |
| MLA | Huang, Zilin et al. "NONCONVEX REGULARIZER AND HOMOTOPY-BASED SPARSE OPTIMIZATION: CONVERGENT ALGORITHMS AND APPLICATIONS" . | JOURNAL OF INDUSTRIAL AND MANAGEMENT OPTIMIZATION 21 . 5 (2025) : 3541-3579 . |
| APA | Huang, Zilin , Jiang, Lanfan , Cao, Weiwei , Zhu, Wenxing . NONCONVEX REGULARIZER AND HOMOTOPY-BASED SPARSE OPTIMIZATION: CONVERGENT ALGORITHMS AND APPLICATIONS . | JOURNAL OF INDUSTRIAL AND MANAGEMENT OPTIMIZATION , 2025 , 21 (5) , 3541-3579 . |
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With the advancement of semiconductor technologies, the acceleration of advanced EDA algorithms is receiving much attention. However, developing a faster mixed-size placer without hardware acceleration and loss of solution quality is of great challenge. In this article, we propose a novel definition of potential energy for each block for global placement based on an analytical solution of Poisson's equation. A fast approximate computation scheme for partial derivatives of the potential energy is given with considerably less computational loads than existing electrostatics-based placers. Moreover, we propose an effective and efficient occupy-aware macro legalization algorithm. Then, a mixed-size placer named Pplace-MS is developed. Compared to the existing leading mixed-size placer, Pplace-MS on average achieves 2.054 x speedup in single-threaded mode on the same machine and 2.3% reduction of scaled half-perimeter wirelength on the modern mixed-size placement benchmarks. The proposed approach can also be considered accelerated on GPU, as previous works.
Keyword ：
Global placement Global placement macro legalization (mLG) macro legalization (mLG) mixed-size design mixed-size design Poisson's equation Poisson's equation
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| GB/T 7714 | Peng, Keyu , Zhu, Wenxing . Pplace-MS: Methodologically Faster Poisson's Equation-Based Mixed-Size Global Placement [J]. | IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS , 2024 , 43 (2) : 613-626 . |
| MLA | Peng, Keyu et al. "Pplace-MS: Methodologically Faster Poisson's Equation-Based Mixed-Size Global Placement" . | IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 43 . 2 (2024) : 613-626 . |
| APA | Peng, Keyu , Zhu, Wenxing . Pplace-MS: Methodologically Faster Poisson's Equation-Based Mixed-Size Global Placement . | IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS , 2024 , 43 (2) , 613-626 . |
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This article proposes a novel fast analytical method for full chip thermal analysis with reduction from 3-D to 2-D using the effective thermal characteristic length, called stepwise integration separation of variables (SISOV). Unlike the traditional separation of variables (SOV) method, which relies heavily on numerical approximation integration for Fourier series coefficient calculation, the proposed SISOV employs analytical stepwise integration by leveraging the uniform power densities across each block. This analytical technique mitigates discretization errors typically encountered in numerical integration, enhancing the accuracy. To overcome the inefficiencies inherent in the plain SOV method, we propose an adaptive rectangular mesh strategy to discretize the chip. This approach markedly reduces the number of required meshed blocks compared to grid sampling points, leading to a more efficient calculation of coefficients. Finally, the fast SISOV method is applied in the thermal uncertainty quantification (UQ) analysis of the full chip. The numerical results show that the proposed SISOV outperforms the plain SOV method, providing a speedup ranging from 2 to 63 times. Moreover, its accuracy surpasses that of the SOV method, with a mean absolute error (MAE) of just 0.05 K, indicating a substantial improvement. The thermal conductivity UQ analysis reveals that the SISOV method and the plain SOV method can achieve 26 x and 9 x faster performance compared to COMSOL, respectively.
Keyword ：
Adaptive rectangular mesh Adaptive rectangular mesh Fourier series Fourier series full-chip full-chip separation of variables (SOV) separation of variables (SOV) stepwise integration stepwise integration thermal uncertainty quantification (UQ) analysis thermal uncertainty quantification (UQ) analysis
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| GB/T 7714 | Yin, Luqiao , Wang, Ao , Zhu, Wenxing et al. A Stepwise Integration Separation of Variables Solver for Full-Chip Thermal Uncertainty Analysis [J]. | IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY , 2024 , 14 (4) : 630-640 . |
| MLA | Yin, Luqiao et al. "A Stepwise Integration Separation of Variables Solver for Full-Chip Thermal Uncertainty Analysis" . | IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY 14 . 4 (2024) : 630-640 . |
| APA | Yin, Luqiao , Wang, Ao , Zhu, Wenxing , Guo, Aiying , Liu, Jingjing , Tang, Min et al. A Stepwise Integration Separation of Variables Solver for Full-Chip Thermal Uncertainty Analysis . | IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY , 2024 , 14 (4) , 630-640 . |
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In VLSI, a large number of vias may reduce manufacturability, degrade circuit performance, and increase layout area required for interconnection. In this paper, we propose a 3D global router V-GR, which considers minimizing the number of vias. V-GR uses a modified via-aware routing cost that considers the impact of wire density on the via. This cost function is more sensitive to the number of vias. Meanwhile, a novel multi-strategy rip-up & rerouting framework is developed for V-GR to solve the overflowed net, effectively optimizing wire length, overflow, and minimizing the number of vias. The proposed framework first leverages two proprietary routing techniques, namely the 3D monotonic routing and 3D 3-via-stack routing, to control the number of vias and reduce overflow. Additionally, the framework incorporates an RSMT-aware expanded source 3D maze routing algorithm to build routing paths with shorter wire length. Experimental results on the ICCAD'19 contest benchmarks show that, VGR achieves high-quality results, reducing vias by 8% and overflow by 7.5% in the global routing phase. Moreover, to achieve a fair comparison, TritonRoute is used to conduct detailed routing, and Innovus is used to evaluate the final solution. Comparison shows that V-GR achieves 4.7% reduction in vias and 8.7% reduction in DRV, while maintaining almost the same wire length.
Keyword ：
global routing global routing maze routing maze routing rip-up & rerouting rip-up & rerouting via via
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| GB/T 7714 | Zhang, Ping , Yao, Pengju , Li, Xingquan et al. V-GR: 3D Global Routing with Via Minimization and Multi-Strategy Rip-up and Rerouting [J]. | 29TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, ASP-DAC 2024 , 2024 : 963-968 . |
| MLA | Zhang, Ping et al. "V-GR: 3D Global Routing with Via Minimization and Multi-Strategy Rip-up and Rerouting" . | 29TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, ASP-DAC 2024 (2024) : 963-968 . |
| APA | Zhang, Ping , Yao, Pengju , Li, Xingquan , Yu, Bei , Zhu, Wenxing . V-GR: 3D Global Routing with Via Minimization and Multi-Strategy Rip-up and Rerouting . | 29TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, ASP-DAC 2024 , 2024 , 963-968 . |
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Abstract ：
Clock tree synthesis (CTS) constructs an efficient clock tree, meeting design constraints and minimizing resource usage. It serves as a bridge between placement and routing, facilitating concurrent optimization of multiple design objectives. To construct a clock tree with lower latency and load capacitance while maintaining a specified skew constraint, we introduce skew-latency-load tree (SLLT) which combines the merits of bound skew tree and Steiner shallow-light tree, along with an analysis and demonstration of the boundaries of these two tree types. We propose a method for constructing SLLT, which significantly reduces both the maximum latency and load capacitance compared to previous methods while ensuring skew control. Combining this routing topology generation method, we introduce a hierarchical CTS framework, and it is constructed by integrating partition schemes and buffering optimization techniques. We validate our solution at 28nm process technology, demonstrating superior performance compared to the solutions of OpenROAD and advanced commercial tool. Our approach outperforms in all metrics (max latency, skew, buffer number, clock capacitance), achieving a significant reduction in latency of 29.45% compared to OpenROAD and 6.75% compared to the commercial tool. © 2024 Copyright is held by the owner/author(s). Publication rights licensed to ACM.
Keyword ：
Atomic clocks Atomic clocks Electric clocks Electric clocks Electronic design automation Electronic design automation Integrated circuit design Integrated circuit design Mechanical clocks Mechanical clocks Trees (mathematics) Trees (mathematics)
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| GB/T 7714 | Li, Weiguo , Huang, Zhipeng , Yu, Bei et al. Toward Controllable Hierarchical Clock Tree Synthesis with Skew-Latency-Load Tree [C] . 2024 . |
| MLA | Li, Weiguo et al. "Toward Controllable Hierarchical Clock Tree Synthesis with Skew-Latency-Load Tree" . (2024) . |
| APA | Li, Weiguo , Huang, Zhipeng , Yu, Bei , Zhu, Wenxing , Li, Xingquan . Toward Controllable Hierarchical Clock Tree Synthesis with Skew-Latency-Load Tree . (2024) . |
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Routing is the most time-consuming phase in the physical design of modern integrated circuits. A carefully designed global routing needs to maximize the routability for the detailed routing while minimizing the wire length and the number of vias. In this paper, we propose a gradient ascent algorithm to solve the 3D global routing ILP model. This algorithm uses the Lagrangian-based cost update method that can more accurately reflect congestion for guiding the global router to generate a solution with fewer vias and congestion. In the gradient ascent rip-up and reroute stage, we use a DAG-based multi-pattern routing strategy to handle highly congested nets with constructed multiple routing patterns. Furthermore, we propose a congestion-aware dynamic net ordering algorithm to improve the congestion convergence of the rip-up and rerouting stage. Experimental results on ICCAD'19 contest benchmarks show that, on average our global router obtains high-quality results, reducing the number of vias by over 1% and 370.6% reduction in DRVs compared to CUGR 2.0, and outperforms TritonRoute-WXL's global routing in terms of runtime consumption and the number of vias.
Keyword ：
detailed-routability detailed-routability global routing global routing net ordering net ordering physical design physical design rip-up and reroute rip-up and reroute
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| GB/T 7714 | Jiang, Junkang , Yao, Pengju , Zhu, Wenxing . Detailed-Routability-Driven Global Routing with Lagrangian-Based Rip-up and Rerouting [J]. | 2024 INTERNATIONAL SYMPOSIUM OF ELECTRONICS DESIGN AUTOMATION, ISEDA 2024 , 2024 : 363-368 . |
| MLA | Jiang, Junkang et al. "Detailed-Routability-Driven Global Routing with Lagrangian-Based Rip-up and Rerouting" . | 2024 INTERNATIONAL SYMPOSIUM OF ELECTRONICS DESIGN AUTOMATION, ISEDA 2024 (2024) : 363-368 . |
| APA | Jiang, Junkang , Yao, Pengju , Zhu, Wenxing . Detailed-Routability-Driven Global Routing with Lagrangian-Based Rip-up and Rerouting . | 2024 INTERNATIONAL SYMPOSIUM OF ELECTRONICS DESIGN AUTOMATION, ISEDA 2024 , 2024 , 363-368 . |
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This paper proposes a rectangular approximation method for curved-shape power density to rapidly calculate the temperature profile of the entire chip by using the 2D thermal model with the effective thermal characteristic length. The proposed method employs rectangular blocks to approximate the non-rectangular power density areas, thereby enabling the utilization of stepwise integration for the determination of the cosine series coefficients. In contrast to the conventional grid mesh approach, this rectangular approximation significantly reduces the number of required mesh elements, thus considerably enhancing computational efficiency. Numerical results reveal that the proposed method achieves a speed improvement ranging from 94x to 195x over the traditional grid technique, while maintaining comparable accuracy. Furthermore, the maximum absolute error observed in temperature predictions is limited to a mere 0.37K.
Keyword ：
non-rectangular power density non-rectangular power density Rectangular grid Rectangular grid separation of variables separation of variables stepwise integration stepwise integration thermal analysis thermal analysis
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| GB/T 7714 | Wang, Ao , Yin, Luqiao , Zhu, Wenxing et al. Rectangular Approximation for Curved-Shape Power Density in Chip Thermal Analysis [J]. | 2024 INTERNATIONAL SYMPOSIUM OF ELECTRONICS DESIGN AUTOMATION, ISEDA 2024 , 2024 : 632-636 . |
| MLA | Wang, Ao et al. "Rectangular Approximation for Curved-Shape Power Density in Chip Thermal Analysis" . | 2024 INTERNATIONAL SYMPOSIUM OF ELECTRONICS DESIGN AUTOMATION, ISEDA 2024 (2024) : 632-636 . |
| APA | Wang, Ao , Yin, Luqiao , Zhu, Wenxing , Guo, Aiying , Liu, Jingjing , Tang, Min et al. Rectangular Approximation for Curved-Shape Power Density in Chip Thermal Analysis . | 2024 INTERNATIONAL SYMPOSIUM OF ELECTRONICS DESIGN AUTOMATION, ISEDA 2024 , 2024 , 632-636 . |
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By leveraging the power of open-source software, the EDA tool offers a cost-effective and flexible solution for designers, researchers, and hobbyists alike. Open-source EDA promotes collaboration, innovation, and knowledge sharing within the EDA community. It emphasizes the role of the toolchain in accelerating the development of electronic systems, reducing design costs, and improving design quality. This paper presents an open-source EDA project, iEDA, aiming to build a basic infrastructure for EDA technology evolution and closing the industrial-academic gap in the EDA area. As the foundation for developing EDA tools and researching EDA algorithms and technologies, iEDA is mainly composed of file system, database, manager, operator and interface. To demonstrate the effectiveness of iEDA, we implement and tape out four chips of different scales (from 700k to 500M gates) on different process nodes (110nm and 28nm) with iEDA. iEDA is publicly available on the project home page https://github.com/OSCC-Project/iEDA.
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| GB/T 7714 | Li, Xingquan , Huang, Zengrong , Tao, Simin et al. iEDA: An Open-source infrastructure of EDA [J]. | 29TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, ASP-DAC 2024 , 2024 : 77-82 . |
| MLA | Li, Xingquan et al. "iEDA: An Open-source infrastructure of EDA" . | 29TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, ASP-DAC 2024 (2024) : 77-82 . |
| APA | Li, Xingquan , Huang, Zengrong , Tao, Simin , Huang, Zhipeng , Zhuang, Chunan , Wang, Hao et al. iEDA: An Open-source infrastructure of EDA . | 29TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, ASP-DAC 2024 , 2024 , 77-82 . |
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To achieve a better partitioning of VLSI circuit, re-clustering and discrete optimization are applied to the k-way partitioning algorithm. Firstly, re-clustering is used to reduce the scale of hypergraph, i.e., the rating function value between two vertices is calculated according to the given partitionings, and vertices are clustered according to the magnitude of the rating function values. Secondly, the hypergraph is converted to a star graph, and the k-way partitioning problem is transformed to an unconstrained discrete optimization problem. In turn, an algorithm is designed to iteratively move the vertices with the largest gain. During the solution process, the balancing constraints are relaxed, allowing a solution to be temporarily in the infeasible region, which expands the solution space of the problem. The proposed algorithm, hMETIS-Kway and KaHyPar-K are tested on the same platform on the ISPD98 test benchmarks, and the min-cut and running time are compared. Experimental results show that, the proposed algorithm is superior to hMETIS-Kway, especially when k=2, for which the min-cut is reduced by 0.173 and the runtime is sped up by 0.706. The proposed algorithm has almost the same improvement effect over KaHyPar-K. © 2024 Institute of Computing Technology. All rights reserved.
Keyword ：
Clustering algorithms Clustering algorithms Graph theory Graph theory Iterative methods Iterative methods Optimization Optimization
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| GB/T 7714 | Pingmei, Pan , Xintian, Liu , Xingquan, Li et al. k-Way Partitioning Algorithm Based on Re-Clustering and Discrete Optimization [J]. | Journal of Computer-Aided Design and Computer Graphics , 2024 , 36 (3) : 473-484 . |
| MLA | Pingmei, Pan et al. "k-Way Partitioning Algorithm Based on Re-Clustering and Discrete Optimization" . | Journal of Computer-Aided Design and Computer Graphics 36 . 3 (2024) : 473-484 . |
| APA | Pingmei, Pan , Xintian, Liu , Xingquan, Li , Wenxing, Zhu . k-Way Partitioning Algorithm Based on Re-Clustering and Discrete Optimization . | Journal of Computer-Aided Design and Computer Graphics , 2024 , 36 (3) , 473-484 . |
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Gate sizing and buffer insertion for timing optimization are performed extensively in electronic design automation (EDA) flows. Both of them aim to adjust the upstream and downstream capacitances of gates/buffers to minimize delay. However, most of existing work focuses on gate sizing or buffer insertion independently. This paper proposes a learning -based timing optimization framework, AiTO, that combines reinforcement learning with graph neural network, to perform simultaneously gate sizing and buffer insertion. We model buffer insertion as a special gate sizing by determining possible buffer locations in advance and treating the buffer insertion and gate sizing as an RL process. Experimental results on 10 real designs (28-nm and 110-nm) show that, AiTO can achieve better worst negative slack (WNS) optimization results than OpenROAD while being able to improve the results of the commercial tool, Innovus, to some extent. Moreover, ablation studies demonstrate the benefits of performing simultaneous gate sizing and buffer insertion for timing optimization.
Keyword ：
Buffer insertion Buffer insertion Gate sizing Gate sizing Graph neural network Graph neural network Reinforcement learning Reinforcement learning Timing optimization Timing optimization
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| GB/T 7714 | Wu, Hongxi , Huang, Zhipeng , Li, Xingquan et al. AiTO: Simultaneous gate sizing and buffer insertion for timing optimization with GNNs and RL [J]. | INTEGRATION-THE VLSI JOURNAL , 2024 , 98 . |
| MLA | Wu, Hongxi et al. "AiTO: Simultaneous gate sizing and buffer insertion for timing optimization with GNNs and RL" . | INTEGRATION-THE VLSI JOURNAL 98 (2024) . |
| APA | Wu, Hongxi , Huang, Zhipeng , Li, Xingquan , Zhu, Wenxing . AiTO: Simultaneous gate sizing and buffer insertion for timing optimization with GNNs and RL . | INTEGRATION-THE VLSI JOURNAL , 2024 , 98 . |
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