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学者姓名：朱文兴
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Abstract ：
. Non-convex optimization regularized with a sparsity function has many applications in machine learning and other fields. Non-convex relaxation of the sparsity function often leads to more effective sparse optimization algorithms. In this paper, we propose a new weighted regularizer to approximate the sparsity function, and derive a weighted thresholding operator for the sparse optimization problem with the regularizer. Then, iterative weighted thresholding algorithms are designed, followed with an acceleration by using Nesterov's acceleration method and non-monotone line search. Under the Kurdyka- Lojasiewicz (KL) property, the smoothness and the appropriate convexity assumptions, we prove that the two algorithms are convergent and the convergence rates are O(1/k) and O(1/k2) respectively, where k is the iteration counter. Moreover, we develop convergent practical homotopy algorithms by invoking the two iterative weighted thresholding algorithms as subroutines respectively. A series of numerical experiments demonstrate that our algorithms are superior in both average recovery rate and average running time for the sparse recovery problem, and are competitive in solution quality and average running time for the logistic regression problem, compared to state-of-the-art algorithms.
Keyword ：
homotopy technique homotopy technique iterative weighted thresholding algorithm iterative weighted thresholding algorithm sparse solution sparse solution weighted regularizer weighted regularizer
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| GB/T 7714 | Huang, Zilin , Jiang, Lanfan , Cao, Weiwei et al. NONCONVEX REGULARIZER AND HOMOTOPY-BASED SPARSE OPTIMIZATION: CONVERGENT ALGORITHMS AND APPLICATIONS [J]. | JOURNAL OF INDUSTRIAL AND MANAGEMENT OPTIMIZATION , 2025 . |
| MLA | Huang, Zilin et al. "NONCONVEX REGULARIZER AND HOMOTOPY-BASED SPARSE OPTIMIZATION: CONVERGENT ALGORITHMS AND APPLICATIONS" . | JOURNAL OF INDUSTRIAL AND MANAGEMENT OPTIMIZATION (2025) . |
| APA | Huang, Zilin , Jiang, Lanfan , Cao, Weiwei , Zhu, Wenxing . NONCONVEX REGULARIZER AND HOMOTOPY-BASED SPARSE OPTIMIZATION: CONVERGENT ALGORITHMS AND APPLICATIONS . | JOURNAL OF INDUSTRIAL AND MANAGEMENT OPTIMIZATION , 2025 . |
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Gate sizing and buffer insertion for timing optimization are performed extensively in electronic design automation (EDA) flows. Both of them aim to adjust the upstream and downstream capacitances of gates/buffers to minimize delay. However, most of existing work focuses on gate sizing or buffer insertion independently. This paper proposes a learning -based timing optimization framework, AiTO, that combines reinforcement learning with graph neural network, to perform simultaneously gate sizing and buffer insertion. We model buffer insertion as a special gate sizing by determining possible buffer locations in advance and treating the buffer insertion and gate sizing as an RL process. Experimental results on 10 real designs (28-nm and 110-nm) show that, AiTO can achieve better worst negative slack (WNS) optimization results than OpenROAD while being able to improve the results of the commercial tool, Innovus, to some extent. Moreover, ablation studies demonstrate the benefits of performing simultaneous gate sizing and buffer insertion for timing optimization.
Keyword ：
Buffer insertion Buffer insertion Gate sizing Gate sizing Graph neural network Graph neural network Reinforcement learning Reinforcement learning Timing optimization Timing optimization
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| GB/T 7714 | Wu, Hongxi , Huang, Zhipeng , Li, Xingquan et al. AiTO: Simultaneous gate sizing and buffer insertion for timing optimization with GNNs and RL [J]. | INTEGRATION-THE VLSI JOURNAL , 2024 , 98 . |
| MLA | Wu, Hongxi et al. "AiTO: Simultaneous gate sizing and buffer insertion for timing optimization with GNNs and RL" . | INTEGRATION-THE VLSI JOURNAL 98 (2024) . |
| APA | Wu, Hongxi , Huang, Zhipeng , Li, Xingquan , Zhu, Wenxing . AiTO: Simultaneous gate sizing and buffer insertion for timing optimization with GNNs and RL . | INTEGRATION-THE VLSI JOURNAL , 2024 , 98 . |
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为了寻得集成电路更优的k路划分,提出将再聚类和离散优化应用于k路划分算法.首先利用再聚类缩小超图规模,即根据给定划分计算顶点间的评级函数值,依据取值大小进行顶点聚类;然后将超图转换为星型图,并将k路划分问题转换为无约束的离散优化问题;进而设计一个算法迭代移动增益值最大的顶点,在算法求解过程中放宽平衡约束,允许暂时处于不可行域的解,扩大问题的求解空间.在同一平台上使用ISPD98电路测试基准对所提算法、hMETIS-Kway和KaHyPar-K进行测试,并比较最小割值和运行时间.实验结果表明该算法优于hMETIS-Kway,特别是在k=2时,最小割值减少了0.173,速度提升了0.706.此外,该算法对KaHyPar-K也有相应的改进效果.
Keyword ：
k路划分 k路划分 最小割 最小割 离散优化 离散优化 超图聚类 超图聚类
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| GB/T 7714 | 潘萍梅 , 刘欣恬 , 李兴权 et al. 基于再聚类和离散优化的k路划分算法 [J]. | 计算机辅助设计与图形学学报 , 2024 , 36 (03) : 473-484 . |
| MLA | 潘萍梅 et al. "基于再聚类和离散优化的k路划分算法" . | 计算机辅助设计与图形学学报 36 . 03 (2024) : 473-484 . |
| APA | 潘萍梅 , 刘欣恬 , 李兴权 , 朱文兴 . 基于再聚类和离散优化的k路划分算法 . | 计算机辅助设计与图形学学报 , 2024 , 36 (03) , 473-484 . |
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Routing is the most time-consuming phase in the physical design of modern integrated circuits. A carefully designed global routing needs to maximize the routability for the detailed routing while minimizing the wire length and the number of vias. In this paper, we propose a gradient ascent algorithm to solve the 3D global routing ILP model. This algorithm uses the Lagrangian-based cost update method that can more accurately reflect congestion for guiding the global router to generate a solution with fewer vias and congestion. In the gradient ascent rip-up and reroute stage, we use a DAG-based multi-pattern routing strategy to handle highly congested nets with constructed multiple routing patterns. Furthermore, we propose a congestion-aware dynamic net ordering algorithm to improve the congestion convergence of the rip-up and rerouting stage. Experimental results on ICCAD'19 contest benchmarks show that, on average our global router obtains high-quality results, reducing the number of vias by over 1% and 370.6% reduction in DRVs compared to CUGR 2.0, and outperforms TritonRoute-WXL's global routing in terms of runtime consumption and the number of vias.
Keyword ：
detailed-routability detailed-routability global routing global routing net ordering net ordering physical design physical design rip-up and reroute rip-up and reroute
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| GB/T 7714 | Jiang, Junkang , Yao, Pengju , Zhu, Wenxing . Detailed-Routability-Driven Global Routing with Lagrangian-Based Rip-up and Rerouting [J]. | 2024 INTERNATIONAL SYMPOSIUM OF ELECTRONICS DESIGN AUTOMATION, ISEDA 2024 , 2024 : 363-368 . |
| MLA | Jiang, Junkang et al. "Detailed-Routability-Driven Global Routing with Lagrangian-Based Rip-up and Rerouting" . | 2024 INTERNATIONAL SYMPOSIUM OF ELECTRONICS DESIGN AUTOMATION, ISEDA 2024 (2024) : 363-368 . |
| APA | Jiang, Junkang , Yao, Pengju , Zhu, Wenxing . Detailed-Routability-Driven Global Routing with Lagrangian-Based Rip-up and Rerouting . | 2024 INTERNATIONAL SYMPOSIUM OF ELECTRONICS DESIGN AUTOMATION, ISEDA 2024 , 2024 , 363-368 . |
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Thermal issues are becoming increasingly critical due to rising power densities in high-performance chip design. The need for fast and precise full-chip thermal analysis is evident. Although machine learning (ML)-based methods have been widely used in thermal simulation, their training time remains a challenge. In this paper, we proposed a novel physics-informed separation of variables solver (PISOV) to significantly reduce training time for fast full-chip thermal analysis. Inspired by the recently proposed ThermPINN, we employ a least-square regression method to calculate the unknown coefficients of the cosine series. The proposed PISOV method combines physics-informed neural network (PINN) and separation of variables (SOV) methods. Due to the matrix-solving method of PISOV, its speed is much faster than that of ThermPINN. On top of PISOV, we parameterize effective convection coefficients and power values for surrogate model-based uncertainty quantification (UQ) analysis by using neural networks, a task that cannot be accomplished by the SOV method. In the parameterized PISOV, we only need to calculate once to obtain all parameterized results of the hyperdimensional PDEs. Additionally, we study the impact of sampling methods (such as grid, uniform, Sobol, Latin Hypercube Sampling(LHS), Halton, and Hammersly) and hybrid sampling methods on the accuracy of PISOV and parameterized PISOV. Numerical results show that PISOV can achieve a speedup of 245×, and 104× over ThermPINN, and PINN, respectively. Among different sampling methods, the Hammersley sampling method yields the best accuracy. © 1982-2012 IEEE.
Keyword ：
Full-chip Full-chip parameterization technique parameterization technique physics-informed separation of variables method physics-informed separation of variables method thermal analysis thermal analysis training time training time
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| GB/T 7714 | Chen, L. , Zhu, W. , Tang, M. et al. PISOV: Physics-Informed Separation of Variables Solvers for Full-Chip Thermal Analysis [J]. | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems , 2024 . |
| MLA | Chen, L. et al. "PISOV: Physics-Informed Separation of Variables Solvers for Full-Chip Thermal Analysis" . | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (2024) . |
| APA | Chen, L. , Zhu, W. , Tang, M. , Tan, S.X.-D. , Mao, J.-F. , Zhang, J. . PISOV: Physics-Informed Separation of Variables Solvers for Full-Chip Thermal Analysis . | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems , 2024 . |
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Timing-driven routing is crucial in complex circuit design. Existing shallow-light Steiner tree construction methods balance between wire length (WL) and source-sink path length (PL) but lack in delay. Conversely, previous delay-driven methods prioritize delay but result in longer WL and PL, making them sub-optimal. In this paper, we show that simultaneously reducing the WL and PL can effectively reduce the delay. Furthermore, we investigate how delay changes during the reduction of PL. Guided by the theoretical findings, we develop a rectilinear shallow-light Steiner tree construction algorithm designed to reduce delay meanwhile maintaining a bounded WL. Furthermore, a delay-driven edge shifting algorithm is proposed to fine-tune the trees topology, further reducing delay. We show that our proposed edge shifting algorithm can return a local Pareto optimal solution when repeatedly applied. Experimental results show that our algorithm achieves the lowest total delay compared to previous methods while maintaining competitive WL. Moreover, for nets with pins that have timing information, our algorithm can generate the most suitable Steiner Tree based on the timing information. In addition, extended experiments highlight the positive impact of constructing rectilinear Steiner trees with minimized total delay. Our codes will be available at https://github.com/Whx97/Delay-driven-Steiner-Tree. © 1982-2012 IEEE.
Keyword ：
Elmore Delay Elmore Delay Rectilinear Steiner Tree Rectilinear Steiner Tree Timing Optimization Timing Optimization
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| GB/T 7714 | Wu, H. , Li, X. , Chen, L. et al. Delay-Driven Rectilinear Steiner Tree Construction [J]. | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems , 2024 . |
| MLA | Wu, H. et al. "Delay-Driven Rectilinear Steiner Tree Construction" . | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (2024) . |
| APA | Wu, H. , Li, X. , Chen, L. , Yu, B. , Zhu, W. . Delay-Driven Rectilinear Steiner Tree Construction . | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems , 2024 . |
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With the advancement of semiconductor technologies, the acceleration of advanced EDA algorithms is receiving much attention. However, developing a faster mixed-size placer without hardware acceleration and loss of solution quality is of great challenge. In this article, we propose a novel definition of potential energy for each block for global placement based on an analytical solution of Poisson's equation. A fast approximate computation scheme for partial derivatives of the potential energy is given with considerably less computational loads than existing electrostatics-based placers. Moreover, we propose an effective and efficient occupy-aware macro legalization algorithm. Then, a mixed-size placer named Pplace-MS is developed. Compared to the existing leading mixed-size placer, Pplace-MS on average achieves 2.054 x speedup in single-threaded mode on the same machine and 2.3% reduction of scaled half-perimeter wirelength on the modern mixed-size placement benchmarks. The proposed approach can also be considered accelerated on GPU, as previous works.
Keyword ：
Global placement Global placement macro legalization (mLG) macro legalization (mLG) mixed-size design mixed-size design Poisson's equation Poisson's equation
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| GB/T 7714 | Peng, Keyu , Zhu, Wenxing . Pplace-MS: Methodologically Faster Poisson's Equation-Based Mixed-Size Global Placement [J]. | IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS , 2024 , 43 (2) : 613-626 . |
| MLA | Peng, Keyu et al. "Pplace-MS: Methodologically Faster Poisson's Equation-Based Mixed-Size Global Placement" . | IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 43 . 2 (2024) : 613-626 . |
| APA | Peng, Keyu , Zhu, Wenxing . Pplace-MS: Methodologically Faster Poisson's Equation-Based Mixed-Size Global Placement . | IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS , 2024 , 43 (2) , 613-626 . |
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Taking advantage of the natural grouping structure inside data, group sparse optimization can effectively improve the efficiency and stability of high-dimensional data analysis, and it has wide applications in a variety of fields such as machine learning, signal processing, and bioinformatics. Although there has been a lot of progress, it is still a challenge to construct a group sparse-inducing function with good properties and to identify significant groups. This article aims to address the group-sparsity-constrained minimization problem. We convert the problem to an equivalent weighted & ell;(p,q)-norm (p>0,0<q <= 1) constrained optimization model, instead of its relaxation or approximation problem. Then, by applying the proximal gradient method, a solution method with theoretical convergence analysis is developed. Moreover, based on the properties proved in the Lagrangian dual framework, the homotopy technique is employed to cope with the parameter tuning task and to ensure that the output of the proposed homotopy algorithm is an $L$ -stationary point of the original problem. The proposed weighted framework, with the central idea of identifying important groups, is compatible with a wide range of support set identification strategies, which can better meet the needs of different applications and improve the robustness of the model in practice. Both simulated and real data experiments demonstrate the superiority of the proposed method in terms of group feature selection accuracy and computational efficiency. Extensive experimental results in application areas such as compressed sensing, image recognition, and classifier design show that our method has great potential in a wide range of applications. Our codes will be available at https://github.com/jianglanfan/HIWT-GSC.
Keyword ：
Group sparse Group sparse homotopy homotopy Indexes Indexes iterative-weighted thresholding (IWT) iterative-weighted thresholding (IWT) Learning systems Learning systems Minimization Minimization non-convex optimization non-convex optimization Optimization Optimization Optimization models Optimization models proximal gradient proximal gradient Robustness Robustness sparse optimization sparse optimization Vectors Vectors
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| GB/T 7714 | Jiang, Lanfan , Huang, Zilin , Chen, Yu et al. Iterative-Weighted Thresholding Method for Group-Sparsity-Constrained Optimization With Applications [J]. | IEEE TRANSACTIONS ON NEURAL NETWORKS AND LEARNING SYSTEMS , 2024 . |
| MLA | Jiang, Lanfan et al. "Iterative-Weighted Thresholding Method for Group-Sparsity-Constrained Optimization With Applications" . | IEEE TRANSACTIONS ON NEURAL NETWORKS AND LEARNING SYSTEMS (2024) . |
| APA | Jiang, Lanfan , Huang, Zilin , Chen, Yu , Zhu, Wenxing . Iterative-Weighted Thresholding Method for Group-Sparsity-Constrained Optimization With Applications . | IEEE TRANSACTIONS ON NEURAL NETWORKS AND LEARNING SYSTEMS , 2024 . |
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By leveraging the power of open-source software, the EDA tool offers a cost-effective and flexible solution for designers, researchers, and hobbyists alike. Open-source EDA promotes collaboration, innovation, and knowledge sharing within the EDA community. It emphasizes the role of the toolchain in accelerating the development of electronic systems, reducing design costs, and improving design quality. This paper presents an open-source EDA project, iEDA, aiming to build a basic infrastructure for EDA technology evolution and closing the industrial-academic gap in the EDA area. As the foundation for developing EDA tools and researching EDA algorithms and technologies, iEDA is mainly composed of file system, database, manager, operator and interface. To demonstrate the effectiveness of iEDA, we implement and tape out four chips of different scales (from 700k to 500M gates) on different process nodes (110nm and 28nm) with iEDA. iEDA is publicly available on the project home page https://github.com/OSCC-Project/iEDA.
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| GB/T 7714 | Li, Xingquan , Huang, Zengrong , Tao, Simin et al. iEDA: An Open-source infrastructure of EDA [J]. | 29TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, ASP-DAC 2024 , 2024 : 77-82 . |
| MLA | Li, Xingquan et al. "iEDA: An Open-source infrastructure of EDA" . | 29TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, ASP-DAC 2024 (2024) : 77-82 . |
| APA | Li, Xingquan , Huang, Zengrong , Tao, Simin , Huang, Zhipeng , Zhuang, Chunan , Wang, Hao et al. iEDA: An Open-source infrastructure of EDA . | 29TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE, ASP-DAC 2024 , 2024 , 77-82 . |
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This paper proposes a rectangular approximation method for curved-shape power density to rapidly calculate the temperature profile of the entire chip by using the 2D thermal model with the effective thermal characteristic length. The proposed method employs rectangular blocks to approximate the non-rectangular power density areas, thereby enabling the utilization of stepwise integration for the determination of the cosine series coefficients. In contrast to the conventional grid mesh approach, this rectangular approximation significantly reduces the number of required mesh elements, thus considerably enhancing computational efficiency. Numerical results reveal that the proposed method achieves a speed improvement ranging from 94×to 195× over the traditional grid technique, while maintaining comparable accuracy. Furthermore, the maximum absolute error observed in temperature predictions is limited to a mere 0.37K. © 2024 IEEE.
Keyword ：
Critical temperature Critical temperature Mesh generation Mesh generation Thermal modeling Thermal modeling
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| GB/T 7714 | Wang, Ao , Yin, Luqiao , Zhu, Wenxing et al. Rectangular Approximation for Curved-Shape Power Density in Chip Thermal Analysis [C] . 2024 : 632-636 . |
| MLA | Wang, Ao et al. "Rectangular Approximation for Curved-Shape Power Density in Chip Thermal Analysis" . (2024) : 632-636 . |
| APA | Wang, Ao , Yin, Luqiao , Zhu, Wenxing , Guo, Aiying , Liu, Jingjing , Tang, Min et al. Rectangular Approximation for Curved-Shape Power Density in Chip Thermal Analysis . (2024) : 632-636 . |
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