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学者姓名：杨秀芝
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Abstract ：
本发明涉及一种基于HEVC标准的帧内预测模式并行硬件方法。该方法通过合理分配模式并行的方案，在硬件实现的过程中可以降低硬件复杂度，节省硬件资源，在流水线设计下，在5500个时钟周期内就能完成一个CTU的帧内预测。
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| GB/T 7714 | 林志坚 , 丁永强 , 杨秀芝 et al. 一种基于HEVC标准的帧内预测模式并行硬件方法 : CN202111545047.2[P]. | 2021-12-16 00:00:00 . |
| MLA | 林志坚 et al. "一种基于HEVC标准的帧内预测模式并行硬件方法" : CN202111545047.2. | 2021-12-16 00:00:00 . |
| APA | 林志坚 , 丁永强 , 杨秀芝 , 程勇 . 一种基于HEVC标准的帧内预测模式并行硬件方法 : CN202111545047.2. | 2021-12-16 00:00:00 . |
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Recently, several in-loop filtering algorithms based on convolutional neural network (CNN) have been proposed to improve the efficiency of HEVC (High Efficiency Video Coding). Conventional CNN-based filters only apply a single model to the whole image, which cannot adapt well to all local features from the image. To solve this problem, an in-loop filtering algorithm based on a dynamic convolutional capsule network (DCC-net) is proposed, which embeds localized dynamic routing and dynamic segmentation algorithms into capsule network, and integrate them into the HEVC hybrid video coding framework as a new in-loop filter. The proposed method brings average 7.9% and 5.9% BD-BR reductions under all intra (AI) and random access (RA) configurations, respectively, as well as, 0.4 dB and 0.2 dB BD-PSNR gains, respectively. In addition, the proposed algorithm has an outstanding performance in terms of time efficiency.
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| GB/T 7714 | Su, LiChao , Cao, Mengqing , Yu, Yue et al. Dynamic convolutional capsule network for In-loop filtering in HEVC video codec [J]. | IET IMAGE PROCESSING , 2022 , 17 (2) : 439-449 . |
| MLA | Su, LiChao et al. "Dynamic convolutional capsule network for In-loop filtering in HEVC video codec" . | IET IMAGE PROCESSING 17 . 2 (2022) : 439-449 . |
| APA | Su, LiChao , Cao, Mengqing , Yu, Yue , Chen, Jian , Yang, XiuZhi , Wu, Dapeng . Dynamic convolutional capsule network for In-loop filtering in HEVC video codec . | IET IMAGE PROCESSING , 2022 , 17 (2) , 439-449 . |
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Recently, several convolutional neural network (CNN)-based in-loop filtering algorithms are proposed to improve the high efficiency video coding (HEVC). However, regular CNN-based filters can only apply a single model to the whole image, but a single model usually cannot adapt well to all local features in the image. To solve this problem, we propose an inloop filtering algorithm based on convolutional capsule network (CC-net), and adapt it into the HEVC hybrid video coding framework as a new in-loop filter. This article is the first to apply capsule to the filtering work of video encoding, which is proposed to use localized dynamic routing algorithm to improve the self-adaptability of the filter to different local features in the image, and we integrate the model into HEVC encoding loop. Experimentally, our proposed method brings average 7.9%, 5.4% and 4.1% BD-BR reductions under all intra, random access and low-delay P configurations, respectively, as well as, 0.4dB, 0.2dB and 0.2dB BD-PSNR gains respectively. © 2021 IEEE.
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| GB/T 7714 | Cao, Mengqing , Yu, Yue , Chen, Jian et al. Convolutional Capsule Network Based in-Loop Filter for HEVC [C] . 2022 : 1451-1457 . |
| MLA | Cao, Mengqing et al. "Convolutional Capsule Network Based in-Loop Filter for HEVC" . (2022) : 1451-1457 . |
| APA | Cao, Mengqing , Yu, Yue , Chen, Jian , Yang, Xiuzhi , Chen, Zhifeng . Convolutional Capsule Network Based in-Loop Filter for HEVC . (2022) : 1451-1457 . |
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为实现"立德树人"的教育教学目标,守好课堂一道渠,有必要将思政元素引入《数字电路》教学中.本文首先说明课程教学内容中的思政元素;接着从以情优教、线上线下混合式教学和任务驱动法三方面阐述课程思政如何进课堂;最后探讨课程评价方式对课程思政积极的影响.实践结果表明,借有形的知识传授来照亮无形的价值引领,可以达到知识教育和思政教育的有机统一.
Keyword ：
以情优教 以情优教 数字电路 数字电路 课程思政 课程思政
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| GB/T 7714 | 许秀英 , 杨秀芝 , 陈建 . 数字电路课程思政的探索与实践 [J]. | 福建电脑 , 2022 , 38 (2) : 115-118 . |
| MLA | 许秀英 et al. "数字电路课程思政的探索与实践" . | 福建电脑 38 . 2 (2022) : 115-118 . |
| APA | 许秀英 , 杨秀芝 , 陈建 . 数字电路课程思政的探索与实践 . | 福建电脑 , 2022 , 38 (2) , 115-118 . |
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Thanks to its flexible coding structure, high-efficiency video coding (HEVC) can save more coding bit rates than the previous standard, H.264. However, it also increases the complexity of integer-pixel motion estimation (IME). To speed up the encoding process, we propose a parallel spiral search (PSS) algorithm, which features the following characteristics and advantages. First, the proposed algorithm is hardware-friendly. PSS has both a fix search order that cuts the correlation between search points and a high data reuse level that facilitates the pipeline application in hardware implementation. Second, the PSS algorithm processes all prediction units (PU) blocks in parallel, which speeds up the RD calculation. Finally, the early termination strategy is proposed to end the search for unnecessary search points and further reduce search time. Experimental results show that the proposed algorithm outperforms other popular hardware-oriented IME algorithms in terms of coding speed, with the same loss of RD performance. Compared with the default full search algorithm (FSA) in the HEVC test model HM-16.7, the proposed algorithm achieves average time saving ratio of up to 92.55%, with BD-PSNR loss of 0.056 dB and an increase by 1.38% in terms of BD-BR.
Keyword ：
Hardware-friendly motion estimation Hardware-friendly motion estimation HEVC HEVC Inter prediction Inter prediction Parallel spiral search Parallel spiral search
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| GB/T 7714 | Shi, Long-Zhao , Zhang, Zhiyong , Luo, Long et al. Parallel spiral search algorithm applied to integer motion estimation [J]. | SIGNAL PROCESSING-IMAGE COMMUNICATION , 2021 , 95 . |
| MLA | Shi, Long-Zhao et al. "Parallel spiral search algorithm applied to integer motion estimation" . | SIGNAL PROCESSING-IMAGE COMMUNICATION 95 (2021) . |
| APA | Shi, Long-Zhao , Zhang, Zhiyong , Luo, Long , Yang, Xiuzhi , Chen, Zhifeng , Yang, Xiaoling et al. Parallel spiral search algorithm applied to integer motion estimation . | SIGNAL PROCESSING-IMAGE COMMUNICATION , 2021 , 95 . |
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尽管新一代视频编码标准(HEVC)显著提升了对视频信号的压缩效率,但却是以大幅增加编码计算复杂度为代价的.为了降低HEVC的复杂度,本文提出了一种基于自下而上编码的帧内预测快速算法.这种算法针对相邻层的预测单元(PU)块纹理的相关性,统计分析相邻深度层PU最佳模式间的关联,对进入粗略模式判决(RMD)的模式提前筛选,从而减少模式选择的复杂度.结果表明,本文算法在保证了性能的前提下,与原硬件实现方案相比,可以节省大约36.17％的预测时间.
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| GB/T 7714 | 程勇 , 杨秀芝 , 肖帅 . 基于自下而上的帧内硬件实现方法的研究 [J]. | 广播电视网络 , 2021 , 28 (5) : 105-109 . |
| MLA | 程勇 et al. "基于自下而上的帧内硬件实现方法的研究" . | 广播电视网络 28 . 5 (2021) : 105-109 . |
| APA | 程勇 , 杨秀芝 , 肖帅 . 基于自下而上的帧内硬件实现方法的研究 . | 广播电视网络 , 2021 , 28 (5) , 105-109 . |
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为满足4K分辨率视频的实时编码传输要求,采用基于Xilinx?Zynq?UltraScale+MPSoC?EV系列芯片进行设计,制作了一种双路4K视频实时编码传输系统,该系统在FPGA的PL端实现视频的采集与编码,在PS端实现编码后数据的封装和发送.该系统充分利用FPGA和ARM各自的优势实现了高效的视频编码和传输,具有较高的集成度和灵活性.测试结果表明系统运行流畅,能实时编码传输双路4K视频.
Keyword ：
H265/HEVC H265/HEVC Zynq UltraScale+MPSoC EV Zynq UltraScale+MPSoC EV 视频编码 视频编码 高分辨率 高分辨率
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| GB/T 7714 | 李栋 , 吴林煌 , 杨秀芝 . 基于FPGA的双路4K视频编码传输系统 [J]. | 广播电视网络 , 2021 , 28 (2) : 96-98 . |
| MLA | 李栋 et al. "基于FPGA的双路4K视频编码传输系统" . | 广播电视网络 28 . 2 (2021) : 96-98 . |
| APA | 李栋 , 吴林煌 , 杨秀芝 . 基于FPGA的双路4K视频编码传输系统 . | 广播电视网络 , 2021 , 28 (2) , 96-98 . |
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High efficiency video coding is the most widely used video coding standard. It has higher coding performance compared with its predecessor, H.264, but it also has higher computational complexity. Interprediction is the most computationally intensive part of the entire video encoding process. Selecting the optimal interprediction mode by the rate-distortion cost calculation function requires substantial complex calculation and memory access, thus greatly increasing the difficulty of real-time hardware encoding. This study proposes to replace the traditional complex error square sum calculation with an estimation method for distortion and rate. The estimation of distortion uses the Hadamard-transformed sum of absolute transformation difference instead of the complex calculation of the sum of squared difference, whereas the estimation of rate is obtained by weighting the number of prediction units (PUs). The experiment proves that the proposed interprediction rate-distortion cost calculation model can greatly reduce computational complexity when BD-rate is increased by 3.02%. In hardware implementation, the value of rate can be obtained by indexing the number of PUs, and the resource expenditure is small.
Keyword ：
Hardware architecture Hardware architecture High efficiency video coding (HEVC) High efficiency video coding (HEVC) Interprediction Interprediction Rate-distortion optimisation (RDO) Rate-distortion optimisation (RDO)
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| GB/T 7714 | Shi, Long-zhao , Yan, Danyu , Hong, Xiaojian et al. Algorithm optimisation and hardware implementation of interprediction mode decision [J]. | JOURNAL OF REAL-TIME IMAGE PROCESSING , 2020 . |
| MLA | Shi, Long-zhao et al. "Algorithm optimisation and hardware implementation of interprediction mode decision" . | JOURNAL OF REAL-TIME IMAGE PROCESSING (2020) . |
| APA | Shi, Long-zhao , Yan, Danyu , Hong, Xiaojian , Huang, Bo , Yang, Xiuzhi . Algorithm optimisation and hardware implementation of interprediction mode decision . | JOURNAL OF REAL-TIME IMAGE PROCESSING , 2020 . |
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Discrete cosine transform (DCT) is an indispensable module in video codecs and is a major part in many video coding standards including the latest high efficiency video coding (HEVC). As the video resolution increases, both transform sizes and the number of transforms increase continuously which poses challenges to the reusability design especially in hardware implementation. This paper presents reconfigurable transform architecture to flexibly support the reusability of different transform sizes. The proposed architecture maximally reuses the hardware resources by rearranging the order of input data for different transform sizes while still exploiting the butterfly property. Furthermore, this architecture supports reconfigurable throughput according to different hardware resource requirements. By applying the proposed architecture to the field-programmable gate array (FPGA) design of HEVC core transform matrices, the synthesis results show much lower consumption of hardware resources comparing to existing methods in the literature. The implementation in Altera's Stratix III FPGA can operate at 139 MHz and supports real-time processing of 3840 x 2160 ultra-high definition video at a minimum of 45 f/s and up to 359 f/s for different DCT sizes.
Keyword ：
DCT DCT FPGA FPGA HEVC HEVC pine-type reordering pine-type reordering
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| GB/T 7714 | Zheng, Mingkui , Zheng, Jingyi , Chen, Zhifeng et al. A Reconfigurable Architecture for Discrete Cosine Transform in Video Coding [J]. | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY , 2020 , 30 (3) : 810-821 . |
| MLA | Zheng, Mingkui et al. "A Reconfigurable Architecture for Discrete Cosine Transform in Video Coding" . | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY 30 . 3 (2020) : 810-821 . |
| APA | Zheng, Mingkui , Zheng, Jingyi , Chen, Zhifeng , Wu, Linhuang , Yang, Xiuzhi , Ling, Nam . A Reconfigurable Architecture for Discrete Cosine Transform in Video Coding . | IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY , 2020 , 30 (3) , 810-821 . |
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在保证视频编码性能的前提下,为降低硬件实现复杂度、减少硬件资源、提高硬件的处理速度,提出一种新的基于现场可编程门阵列(FPGA)的高效视频编码标准(HEVC)帧内预测硬件结构.设计的硬件结构可以支持64×64到4×4的块大小以及所有的模式预测,而且经过实验,实现一个完整的64×64大小的编码树单元(CTU)的编码过程需要3.3×104左右的周期数,主频能够达到160 MHz.
Keyword ：
哈达玛变换 哈达玛变换 帧内预测 帧内预测 现场可编程门阵列 现场可编程门阵列 硬件结构 硬件结构
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| GB/T 7714 | 杨贺 , 杨秀芝 , 陈建 . 一种新的基于FPGA的HEVC帧内预测硬件结构 [J]. | 福州大学学报（自然科学版） , 2020 , 48 (3) : 318-324 . |
| MLA | 杨贺 et al. "一种新的基于FPGA的HEVC帧内预测硬件结构" . | 福州大学学报（自然科学版） 48 . 3 (2020) : 318-324 . |
| APA | 杨贺 , 杨秀芝 , 陈建 . 一种新的基于FPGA的HEVC帧内预测硬件结构 . | 福州大学学报（自然科学版） , 2020 , 48 (3) , 318-324 . |
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