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Abstract:
A low power hybrid PG_Filter-AGC analog baseband is presented, including a programmable filter (PG_filter) and an auto gain control core (AGC_core). It adopts the digital-plus-analog mixed gain control methodology, resulting in an effective power reduction and a decibel gain error improvement. To further reduce the power of the AGC_core, a low power Variable Gain Amplifier (VGA) adopting sub-threshold design methodology is presented. Furthermore, a self-adaptive threshold voltage compensation (SATC) scheme is proposed to guarantee the good anti-process variation performance for sub-threshold design methodology. The hybrid analog baseband has been fabricated under SMIC 0.18 mu m CMOS process, with a die size of 0.45 mm(2), where the AGC_core occupies an area of 0.28 mm(2). The test results demonstrate a total power of 4.1 mW, where the AGC_core consumes a power of 0.39 mW. A consecutive gain dynamic range of 80 dB, with a decibel gain error small than +/- 0.39 dB, is achieved and the cutoff frequency ranges from 0.5MHz similar to 30 MHz.
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IEICE ELECTRONICS EXPRESS
ISSN: 1349-2543
Year: 2018
Issue: 3
Volume: 15
0 . 5 8 6
JCR@2018
0 . 8 0 0
JCR@2023
ESI Discipline: ENGINEERING;
ESI HC Threshold:170
JCR Journal Grade:4
CAS Journal Grade:4
Cited Count:
WoS CC Cited Count: 2
SCOPUS Cited Count: 2
ESI Highly Cited Papers on the List: 0 Unfold All
WanFang Cited Count:
Chinese Cited Count:
30 Days PV: 5
Affiliated Colleges: