A case study on the scan architecture of dft technique - Details

author：

Lin, Wei (Lin, Wei.) ^[1] (Scholars：林伟) | Huang, Shi-Zhen (Huang, Shi-Zhen.) ^[2] (Scholars：黄世震) | Shi, Wen-Long (Shi, Wen-Long.) ^[3]

Indexed by：

EI Scopus

Abstract：

As　circuit　sizes　grow　ever　larger,　test　data　volume　and　test　application　time　grow　unwieldy　even　in　the　very　efficient　scan　based　designs.　Adaptive　scan　architecture　of　Design　for　Test　(DFT)　technique　is　used　to　reduce　test　application　time　and　test　data　volume.　In　our　research,　we　analyze　the　technique　of　the　scan　test　architecture.　Based　on　the　analysis,　the　adaptive　scan　of　DFT　technique　is　succeeding　applied　to　a　SOC　chip.　Experimental　results　show　that　the　test　cost　of　the　SOC　chip　is　greatly　reduced.　Compared　with　the　original　program,　the　fault　coverage　is　reached　97%,　the　test　data　volume　is　decreased　8.79　times,　the　test　time　is　reduced　almost　6　times.　©　2013　Asian　Network　for　Scientific　Information.

Keyword：

Design for testability Programmable logic controllers Software testing System-on-chip Testing

Community：

[ 1 ] [Lin, Wei]College of Physics and Information Engineering, Fuzhou University, Fuzhou, Fujian, China
[ 2 ] [Lin, Wei]Fujian Key Laboratory of Microelectronics and Integrated Circuits, China
[ 3 ] [Huang, Shi-Zhen]College of Physics and Information Engineering, Fuzhou University, Fuzhou, Fujian, China
[ 4 ] [Huang, Shi-Zhen]Fujian Key Laboratory of Microelectronics and Integrated Circuits, China
[ 5 ] [Shi, Wen-Long]College of Physics and Information Engineering, Fuzhou University, Fuzhou, Fujian, China
[ 6 ] [Shi, Wen-Long]Fujian Key Laboratory of Microelectronics and Integrated Circuits, China