A　modern　field-programmable　gate　array　(FPGA)　often　contains　an　ASIC-like　clocking　architecture　which　is　crucial　to　achieve　better　skew　and　performance.　Existing　conventional　FPGA　placement　algorithms　seldom　consider　clocking　resources,　and　thus　may　lead　to　clock　routing　failures.　To　address　the　special　FPGA　clocking　architecture,　this　article　presents　an　effective　clock-aware　placement　algorithm　for　large-scale　heterogeneous　FPGAs.　Our　algorithm　consists　of　four　major　technologies:　1)　a　combinatorial　clock　fence　region　method　to　effectively　reduce　the　overuse　of　clocking　resources;　2)　a　smoothed　heterogeneous　density　function　to　lead　heterogeneous　blocks　to　desired　sites　and　a　coordinate　transformation　technique　to　facilitate　CLB　cell　spreading;　3)　a　heterogeneous　force　modulation　algorithm　to　stabilize　placement　movement　and　a　hierarchical　contraction　technique　to　remedy　an　insufficiency　of　the　multilevel　placement　framework;　and　4)　a　two-level　clock-aware　packing　and　legalization　scheme　to　generate　an　optimized,　clocking-violation-free　placement.　We　evaluate　our　results　based　on　the　ISPD　2017　Clock-Aware　Placement　Contest　benchmark　suite.　Compared　with　the　state-of-the-art　placers,　the　experimental　results　show　that　our　algorithm　achieves　the　best-routed　wirelength.