To　tackle　the　challenge　of　applying　convolutional　neural　network　(CNN)　in　field-programmable　gate　array　(FPGA)　due　to　its　computational　complexity,　a　high-performance　CNN　hardware　accelerator　based　on　Verilog　hardware　description　language　was　designed,　which　utilizes　a　pipeline　architecture　with　three　parallel　dimensions　including　input　channels,　output　channels,　and　convolution　kernels.　Firstly,　two　multiply-and-accumulate　(MAC)　operations　were　packed　into　one　digital　signal　processing　(DSP)　block　of　FPGA　to　double　the　computation　rate　of　the　CNN　accelerator.　Secondly,　strategies　of　feature　map　block　partitioning　and　special　memory　arrangement　were　proposed　to　optimize　the　total　amount　of　off-chip　access　memory　and　reduce　the　pressure　on　FPGA　bandwidth.　Finally,　an　efficient　computational　array　combining　multiplicative-additive　tree　and　Winograd　fast　convolution　algorithm　was　designed　to　balance　hardware　resource　consumption　and　computational　performance.　The　high　parallel　CNN　accelerator　was　deployed　in　ZU3EG　of　Alinx,　using　the　YOLOv3-tiny　algorithm　as　the　test　object.　The　average　computing　performance　of　the　CNN　accelerator　is　127.5　giga　operations　per　second　(GOPS).　The　experimental　results　show　that　the　hardware　architecture　effectively　improves　the　computational　power　of　CNN　and　provides　better　performance　compared　with　other　existing　schemes　in　terms　of　power　consumption　and　the　efficiency　of　DSPs　and　block　random　access　memory　(BRAMs).　©　2022,　Beijing　University　of　Posts　and　Telecommunications.　All　rights　reserved.