A 28-GHz Current-Mode Inverse-Outphasing Power Amplifier in 65-nm CMOS - Details

author：

Li, Liangfeng (Li, Liangfeng.) ^[1] | Ni, Dongliang (Ni, Dongliang.) ^[2] | Chen, Jiazheng (Chen, Jiazheng.) ^[3] | Huang, Jiwei (Huang, Jiwei.) ^[4]

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Abstract：

In　this　paper,　a　28-GHz　high　efficiency　outphasing　power　amplifier　(PA)　with　Chireix　compensation　in　65-nm　Silicon-On-Insulator　(SOI)　CMOS　technology　is　proposed.　To　improve　the　power-back-off　(PBO)　efficiency,　the　PA　uses　a　current-mode　inverse　outphasing　architecture,　which　supports　compatibility　with　current-mode　PAs,　highly　efficient　active　load　modulation.　Meanwhile,　the　neutralization　capacitor　and　source　degeneration　inductor　technology　is　employed　to　tradeoff　linearity　and　high　efficiency　requirements.　At　28GHz　with　a　supply　voltage　of　2.5/1.2V,　the　complete　outphasing　PA　achieves　a　simulated　saturated　output　power　of　23.8dBm　with　45.1%　power-added　efficiency　(PAE)　and　6dB　back-off　PAE　of　25.2%,　1-dB　compression　output　power　of　21.8dBm,　and　gain　of　16.6dB.　The　simulation　results　also　show　that　the　PA　is　unconditionally　stable　in　the　whole　working　frequency　band.　The　power　amplifier　has　a　layout　size　of　1.02　mm2　and　a　core　area　of　0.46　mm2.　©　2021　IEEE.

Keyword：

CMOS integrated circuits Efficiency Millimeter waves Power amplifiers Silicon on insulator technology Timing circuits

Community：

[ 1 ] [Li, Liangfeng]Fuzhou University, Department of College of Physics and Information Engineering, Fuzhou, China
[ 2 ] [Ni, Dongliang]Fuzhou University, Department of College of Physics and Information Engineering, Fuzhou, China
[ 3 ] [Chen, Jiazheng]Fuzhou University, Department of College of Physics and Information Engineering, Fuzhou, China
[ 4 ] [Huang, Jiwei]Fuzhou University, Department of College of Physics and Information Engineering, Fuzhou, China

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Year： 2021

Page： 268-271

Language： English

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ESI Highly Cited Papers on the List： 0 Unfold All

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30 Days PV： 2

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