As　the　last　stage　of　VLSI　routing,　detailed　routing　should　consider　complicated　design　rules　in　order　to　meet　the　manufacturability　of　chips.　With　the　continuous　development　of　VLSI　technology　node,　the　design　rules　are　changing　and　increasing　which　makes　detailed　routing　a　hard　task.　In　this　paper,　we　present　a　practical　track-assignment-based　detailed　router　to　deal　with　the　most　representative　design　rules　in　modern　designs.　The　proposed　router　consists　of　four　major　stages:　(1)　a　graph-based　track　assignment　algorithm　is　proposed　to　optimize　the　design　rule　violations　of　an　entire　die　area;　(2)　an　effective　rip-up　and　reroute　method　is　used　to　reduce　the　design　rule　violations　in　local　regions;　(3)　a　segment　migration　algorithm　is　proposed　to　reduce　short　violations;　and　(4)　a　stack　via　optimization　technique　is　proposed　to　reduce　minimum　area　violations.　Practical　benchmarks　from　2019　ISPD　contest　are　used　to　evaluate　the　proposed　router.　Compared　with　the　state-of-the-art　detailed　router,　Dr.　CU　2.0,　the　number　of　violations　can　be　reduced　by　up　to　35.11　%　with　an　average　reduction　rate　of　10.08　%.　The　area　of　short　can　be　reduced　by　up　to　61.49　%　with　an　average　reduction　rate　of　44.80　%.　©　2022　EDAA.