The　transformer　model　has　recently　been　a　milestone　in　artificial　intelligence.　The　algorithm　has　enhanced　the　performance　of　tasks　such　as　Machine　Translation　and　Computer　Vision　to　a　level　previously　unattainable.　However,　the　transformer　model　has　a　strong　performance　but　also　requires　a　high　amount　of　memory　overhead　and　enormous　computing　power.　This　significantly　hinders　the　deployment　of　an　energy-efficient　transformer　system.　Due　to　the　high　parallelism,　low　latency,　and　low　power　consumption　of　field-programmable　gate　arrays　(FPGAs)　and　application　specific　integrated　circuits　(ASICs),　they　demonstrate　higher　energy　efficiency　than　Graphics　Processing　Units　(GPUs)　and　Central　Processing　Units　(CPUs).　Therefore,　FPGA　and　ASIC　are　widely　used　to　accelerate　deep　learning　algorithms.　Several　papers　have　addressed　the　issue　of　deploying　the　Transformer　on　dedicated　hardware　for　acceleration,　but　there　is　a　lack　of　comprehensive　studies　in　this　area.　Therefore,　we　summarize　the　transformer　model　compression　algorithm　based　on　the　hardware　accelerator　and　its　implementation　to　provide　a　comprehensive　overview　of　this　research　domain.　This　paper　first　introduces　the　transformer　model　framework　and　computation　process.　Secondly,　a　discussion　of　hardware-friendly　compression　algorithms　based　on　self-attention　and　Transformer　is　provided,　along　with　a　review　of　a　state-of-the-art　hardware　accelerator　framework.　Finally,　we　considered　some　promising　topics　in　transformer　hardware　acceleration,　such　as　a　high-level　design　framework　and　selecting　the　optimum　device　using　reinforcement　learning.