Programmable　switches　empower　stateful　packet　processing,　in　which　incoming　packets　continuously　update　states　in　the　data　plane,　while　applications　in　the　control　plane　read　and　write　states.　However,　since　the　data　plane　and　control　plane　are　separated,　a　consistent　view　of　states　in　both　planes　is　required　for　stateful　packet　processing.　Existing　approaches　suffer　from　either　high　latency　or　low　accuracy.　In　this　paper,　we　propose,　a　framework　that　offers　approximate　state　synchronization　with　low　latency　and　high　accuracy.　To　achieve　low　latency,　directly　transfers　states　between　switch　ASICs　and　the　control　plane　by　bypassing　switch　operating　systems.　To　achieve　high　accuracy,　utilizes　the　resources　in　the　switch　ASIC　to　realize　rate　control　in　state　synchronization,　such　that　it　avoids　potential　state　loss.　It　also　bounds　the　divergence　between　the　states　in　the　data　plane　and　that　in　the　control　plane　under　limited　link　capacity.　We　prototype　on　Barefoot　Tofino　switches.　The　experimental　results　indicate　that　compared　to　existing　approaches,　achieves　order-of-magnitude　latency　reduction　while　maintaining　high　accuracy　of　state　synchronization.　Also,　our　experiments　demonstrate　that　provides　significant　latency　benefits　to　existing　network　management　applications　and　well　preserves　high　application-level　accuracy.