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author:

Zhuang, Hongbin (Zhuang, Hongbin.) [1] | Li, Xiao-Yan (Li, Xiao-Yan.) [2] | Chang, Jou-Ming (Chang, Jou-Ming.) [3] | Wang, Dajin (Wang, Dajin.) [4]

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EI

Abstract:

The k-ary n-cube Qnk is one of the most important interconnection networks for building network-on-chips, data center networks, and parallel computing systems owing to its desirable properties. Since edge faults grow rapidly and the path structure plays a vital role in large-scale networks for parallel computing, fault-tolerant path embedding and its related problems have attracted extensive attention in the literature. However, the existing path embedding approaches usually only focus on the theoretical proofs and produce an n-related linear fault tolerance since they are based on the traditional fault model, which allows all faults to be adjacent to the same node. In this paper, we design an efficient fault-tolerant Hamiltonian path embedding algorithm for enhancing the fault-tolerant capacity of k-ary n-cubes. To facilitate the algorithm, we first introduce a new conditional fault model, named Partitioned Edge Fault model (PEF model). Based on this model, for the k-ary n-cube Qnk with n ≥ 2 and odd k ≥ 3, we explore the existence of a Hamiltonian path in Qnk with large-scale edge faults. Then we give an O(N) algorithm, named HP-PEF, to embed the Hamiltonian path into Qnk under the PEF model, where N is the number of nodes in Qnk. The performance analysis of HP-PEF shows the average path length of adjacent node pairs in the Hamiltonian path constructed by HP-PEF. We also make comparisons to show that our result of edge fault tolerance has exponentially improved other known results. We further experimentally show that HP-PEF can support the dynamic degradation of average success rate of constructing Hamiltonian paths when increasing faulty edges exceed the fault tolerance. © 1990-2012 IEEE.

Keyword:

Electronics packaging Fault tolerance Geometry Hamiltonians Integrated circuit interconnects Interconnection networks (circuit switching) Network-on-chip Three dimensional computer graphics Three dimensional displays Three dimensional integrated circuits

Community:

  • [ 1 ] [Zhuang, Hongbin]Fuzhou University, College of Computer and Data Science, Fuzhou; 350108, China
  • [ 2 ] [Li, Xiao-Yan]Fuzhou University, College of Computer and Data Science, Fuzhou; 350108, China
  • [ 3 ] [Chang, Jou-Ming]National Taipei University of Business, Institute of Information and Decision Sciences, Taipei; 10051, Taiwan
  • [ 4 ] [Wang, Dajin]Montclair State University, Department of Computer Science, Montclair; NJ; 07043, United States

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Source :

IEEE Transactions on Parallel and Distributed Systems

ISSN: 1045-9219

Year: 2023

Issue: 6

Volume: 34

Page: 1802-1815

5 . 6

JCR@2023

5 . 6 0 0

JCR@2023

ESI HC Threshold:32

JCR Journal Grade:1

CAS Journal Grade:1

Cited Count:

WoS CC Cited Count: 0

SCOPUS Cited Count: 2

ESI Highly Cited Papers on the List: 0 Unfold All

WanFang Cited Count:

Chinese Cited Count:

30 Days PV: 1

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