This　paper　proposes　a　pseudo　third-order　discrete-time　delta-sigma　modulator　to　address　the　bottleneck　of　high　resolution　and　low　power　consumption　in　Internet　of　Things　(IoT)　sensors.　This　architecture　embeds　a　first-order　passive　noise-shaping　SAR　(Successive　Approximation　Register)　quantizer　into　a　conventional　second-order　delta-sigma　modulator　to　achieve　stronger　noise-shaping　capabilities.　This　allows　the　system　to　achieve　higher　peak　SQNR　(Signal-to-Quantizing　Noise　Ratio)　at　lower　OSR　(Over　Sampling　Ratio),　effectively　mitigating　the　design　trade-off　between　system　accuracy　and　power　consumption,　while　reducing　the　use　of　active　integrators.　In　response　to　the　high　power　consumption　of　traditional　active　adders　and　the　attenuation　uncertainty　of　passive　adders,　this　paper　proposes　a　novel　feedforward　sum　quantization　circuit.　It　has　the　advantage　of　being　insensitive　to　attenuation　and　reduces　the　driving　pressure　of　the　second　stage　active　integrator,　which　further　reduces　the　power　consumption　of　the　system.　The　proposed　delta-sigma　modulator　is　manufactured　and　tested　using　a　180　nm　CMOS　(Complementary　Metal　Oxide　Semiconductor)　process.　At　a　power　supply　voltage　of　1.4　V,　the　tested　power　consumption　of　the　chip　is　47.2　μW.　With　a　bandwidth　of　8　kHz,　the　DR　(Dynamic　Range),　peak　SNDR　(Signal-to-Noise　and　Distortion　Ratio),　and　SFDR　(Spurious-Free　Dynamic　Range)　of　the　modulator　are　97.2　dB,　96.6　dB,　and　114.4　dB,　respectively.　Therefore,　figure-of-merit　(FoM)　Schreier　and　Walden　for　SNDR　are　178.9　dB　and　0.053　pJ/step.　The　pseudo　third-order　delta-sigma　modulator　proposed　in　this　article　achieves　a　good　balance　between　power　consumption　and　resolution,　providing　a　good　solution　for　low-power　and　high-resolution　modulator　design　in　the　field　of　the　IoTs.　©　2024　Chinese　Institute　of　Electronics.　All　rights　reserved.