Short-channel-length　thin-film　amorphous　oxide　semiconductor　field-effect　transistor　(AOSFET)　two-transistor　zero-capacitor　(2TOC)　gain　cell　(GC)　memories　are　one　of　the　promising　technologies　for　three-dimensional　integrated　memories.　2TOC　with　a　high-threshold　voltage　write　transistor　and　a　low-threshold　voltage　read　transistor　can　achieve　tens　of　thousands　of　seconds　of　retention　time　and　low　power　consumption.　However,　the　low　threshold　voltage　of　the　read　transistor　leads　to　an　increasing　leakage　current　from　the　unselected　data　cells,　which　reduces　the　read　margin.　In　this　paper,　we　propose　using　a　pre-charge　sense　amplifier　(PCSA)　to　reduce　leakage　current　and　enhance　the　read　margin.　A　reference　generation　circuit　is　also　proposed　to　enhance　the　read　accuracy.　The　simulation　results　show　that　the　proposed　PCSA　increases　the　read　margin　to　168　mV.　For　the　large　array　with　128　memory　cells　in　a　column,　a　90　mV　read　margin　can　still　be　achieved　compared　to　the　55　mV　in　the　conventional　SA　setup.　©　2024　IEEE.