Channel-all-around　(CAA)　amorphous　oxide　semiconductor　field-effect　transistors　(AOSFETs)　represent　a　promising　technology　for　next-generation,　low-power,　three-dimensional　integrated　dynamic　random-access　memory　(DRAM)　with　high　density　and　low-temperature　process　compatibility.　In　two-transistor　capacitorless　(2T0C)　CAA　AOSFETs　gain　cells,　the　storage　node　(SN)　parasitic　capacitances　are　governed　by　both　intrinsic　cell　parasitic　and　interconnect　parasitic　capacitances.　This　work　employs　the　partial-element　equivalent　circuit　(PEEC)　method　to　efficiently　extract　parasitic　capacitances　from　large-scale　arrays.　We　systematically　investigate　the　impact　of　these　capacitances　on　the　SN　charge-retention　capability.　Furthermore,　we　propose　two　optimization　methods　that　enhance　the　voltage　consistency　across　a　128-cell　column　to　76.43%.　©　2025　IEEE.