Gate　sizing　and　buffer　insertion　for　timing　optimization　are　performed　extensively　in　electronic　design　automation　(EDA)　flows.　Both　of　them　aim　to　adjust　the　upstream　and　downstream　capacitances　of　gates/buffers　to　minimize　delay.　However,　most　of　existing　work　focuses　on　gate　sizing　or　buffer　insertion　independently.　This　paper　proposes　a　learning　-based　timing　optimization　framework,　AiTO,　that　combines　reinforcement　learning　with　graph　neural　network,　to　perform　simultaneously　gate　sizing　and　buffer　insertion.　We　model　buffer　insertion　as　a　special　gate　sizing　by　determining　possible　buffer　locations　in　advance　and　treating　the　buffer　insertion　and　gate　sizing　as　an　RL　process.　Experimental　results　on　10　real　designs　(28-nm　and　110-nm)　show　that,　AiTO　can　achieve　better　worst　negative　slack　(WNS)　optimization　results　than　OpenROAD　while　being　able　to　improve　the　results　of　the　commercial　tool,　Innovus,　to　some　extent.　Moreover,　ablation　studies　demonstrate　the　benefits　of　performing　simultaneous　gate　sizing　and　buffer　insertion　for　timing　optimization.