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author:

Liu, Genggeng (Liu, Genggeng.) [1] (Scholars:刘耿耿) | Chen, Zhengyang (Chen, Zhengyang.) [2] | Chen, Zhisheng (Chen, Zhisheng.) [3] | Liu, Bowen (Liu, Bowen.) [4] | Zhang, Yu (Zhang, Yu.) [5] | Huang, Xing (Huang, Xing.) [6]

Indexed by:

EI Scopus SCIE

Abstract:

In recent years, microfluidic biochips have been widely applied in various fields of human society. The optimization design of system -architecture based on continuous-flow microfluidic biochips has been widely studied. However, most previous work was based on the traditional chip architecture with dedicated storage, which not only limits the performance of biochips but also increases their manufacturing costs. In order to improve the execution efficiency and reduce the manufacturing cost, a distributed channel-storage architecture can be used to temporarily cache intermediate fluids in idle flow channels. Under this architecture, careful consideration of the volume management of the fluid to be cached is a prerequisite for ensuring the reliability of bioassay results. However, the existing work has not considered the volume management of the fluid to be cached in detail. This may cause the volume of the fluid to not match the capacity of the storage channel, which can contaminate other fluids and lead to incorrect bioassay results or increase the manufacturing cost of biochips due to long storage channels. In this paper, we propose a physical design method for microfluidic biochips that considers the actual volume of fluid while utilizing distributed channel storage. We address this problem by taking a placement and routing co -design strategy throughout the iterative process of the simulated annealing algorithm. Experimental results under multiple benchmarks show that the proposed method can effectively reduce the completion time of bioassays, minimize the flow path length, and decrease the number of intersections.

Keyword:

Actual volume management Distributed channel-storage architecture Microfluidic biochips Physical design

Community:

  • [ 1 ] [Liu, Genggeng]Fuzhou Univ, Coll Comp & Data Sci, Fuzhou 350116, Peoples R China
  • [ 2 ] [Chen, Zhengyang]Fuzhou Univ, Coll Comp & Data Sci, Fuzhou 350116, Peoples R China
  • [ 3 ] [Liu, Bowen]Fuzhou Univ, Coll Comp & Data Sci, Fuzhou 350116, Peoples R China
  • [ 4 ] [Liu, Genggeng]Minist Educ, Engn Res Ctr Big Data Intelligence, Fuzhou 350116, Peoples R China
  • [ 5 ] [Chen, Zhengyang]Minist Educ, Engn Res Ctr Big Data Intelligence, Fuzhou 350116, Peoples R China
  • [ 6 ] [Liu, Bowen]Minist Educ, Engn Res Ctr Big Data Intelligence, Fuzhou 350116, Peoples R China
  • [ 7 ] [Chen, Zhisheng]Xiamen Univ, Sch Informat, Xiamen 361005, Peoples R China
  • [ 8 ] [Huang, Xing]Fuzhou Univ Int Studies & Trade, Key Lab Data Sci & Intelligent Comp, Fuzhou 350202, Peoples R China
  • [ 9 ] [Zhang, Yu]Northwestern Polytech Univ, Sch Comp Sci, Xian 710072, Peoples R China
  • [ 10 ] [Huang, Xing]Northwestern Polytech Univ, Sch Comp Sci, Xian 710072, Peoples R China

Reprint 's Address:

  • [Huang, Xing]Fuzhou Univ Int Studies & Trade, Key Lab Data Sci & Intelligent Comp, Fuzhou 350202, Peoples R China;;

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Source :

INTEGRATION-THE VLSI JOURNAL

ISSN: 0167-9260

Year: 2024

Volume: 98

2 . 2 0 0

JCR@2023

Cited Count:

WoS CC Cited Count:

SCOPUS Cited Count:

ESI Highly Cited Papers on the List: 0 Unfold All

WanFang Cited Count:

Chinese Cited Count:

30 Days PV: 1

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