As　the　miniaturization　of　integrated　circuits　(ICs)　reaches　its　physical　limits,　the　industry　is　entering　a　＇more-than-Moore＇　era,　demanding　new　Electronic　Design　Automation　(EDA)　tools.　Existing　TSV-based　3D　placers　focus　on　minimizing　cuts　while　burgeoning　F2F-bonded　ICs　feature　dense　interconnection　between　two　planar　die.　Towards　this　novel　structure,　we　proposed　an　integrated　adaptation　methodology　upon　mature　one-die-based　placement　strategies.　First,　we　instructively　utilized　a　one-die　placer　to　provide　a　statistical　looking-ahead　net　diagnosis.　The　netlist　henceforth　shall　be　coarsened　topologically　and　geometrically　using　a　multi-level　framework.　Our　multi-objective　gain　formulation　guides　a　level-by-level　refinement　of　the　partition.　This　formulation　considers　factors　like　cut　expectation,　heterogeneous　row　heights,　and　balanced　cell　distribution,　enabling　efficient　incremental　calculations　at　each　level.　Given　the　partition,　we　synchronized　the　behavior　of　analytical　planar　placers　by　balancing　the　density　and　wirelength　objective　function　among　asymmetric　layers.　Finally,　the　result　will　be　further　improved　by　heuristic　detail　placement　of　bonding　terminals　and　a　post-place　partition　adjustment.　Experimental　results　demonstrate　that　our　fine-grained　fusion　of　partitioning　and　placement　techniques　are　competitive　compared　with　the　top　three　winners　of　the　2022　ICCAD　CAD　Contest,　achieving　the　best　normalized　average　wirelength　with　competitive　runtime　under　various　3D　architectural　constraints.　©　2025　Elsevier　B.V.