As　the　design　complexity　keep　increasing,　the　2.5D　FPGA　with　large　logic　capacity　has　become　popular　in　modern　circuit　applications.　A　2.5D　FPGA　consists　of　multiple　dies　connected　through　super　long　lines　(SLLs)　on　an　interposer,　where　each　die　contains　heterogeneous　logic　blocks　and　ASIC-like　clocking　architectures　to　achieve　better　skew　and　timing.　To　address　the　crucial　SLL　issue　and　the　special　clocking　architecture,　this　paper　presents　the　first　analytical　placement　algorithm　for　the　2.5D　FPGA　with　the　objective　of　minimizing　the　numbers　of　inter-die　SLL　signals　and　intra-die　clocking　violations　simultaneously.　Using　a　lifting　dimension　technique,　we　first　formulate　the　2.5D　global　placement　problem　as　a　three-dimensional　continuous　and　differential　minimization　problem,　where　the　SLL-aware　block　distribution　is　modeled　by　3D　Poisson＇s　equation　and　directly　solved　to　obtain　an　analytical　solution.　Then,　we　further　reformulate　the　minimization　problem　as　a　separable　optimization　problem　with　linear　constraints.　Based　on　the　proximal　alternating　direction　method　of　multipliers　(ADMM)　optimization　method,　we　efficiently　optimize　the　separable　subproblems　one　by　one　in　an　alternating　fashion.　Finally,　clock-aware　legalization　and　detailed　placement　are　applied　to　legalize　and　further　improve　our　placement　results.　Compared　with　the　state-of-the-art　work,　experimental　results　show　that　our　algorithm　can　resolve　all　clocking　constraints　and　reduce　the　number　of　SLL　crossing　signals　by　36.9%　with　similar　wirelength　in　comparable　running　time.　©　2019　IEEE.