Charge-domain　computing-in-memory　(CIM)　requires　large　storage　node　(SN)　capacitors　to　achieve　high　computational　accuracy　and　energy　efficiency,　which　fundamentally　limits　the　scalability　of　CIM　arrays.　Although　capacitorless　gain　cells　(GCs)　offer　significantly　higher　array　density,　their　parasitic　capacitances　hinder　practical　CIM　applications.　In　this　work,　we　utilized　the　partial　element　equivalent　circuit　(PEEC)　method　to　efficiently　extract　parasitic　parameters　from　large-scale　two-transistor　capacitorless　(2T0C)　GC　arrays.　We　developed　comprehensive　equivalent　parasitic　models　for　in-array　2TOC　gain　cells,　with　dedicated　optimization　for　both　read　and　write　operations.　Experimental　results　demonstrated　that　parasitic　effects　induce　a　15%　degradation　in　SN　voltage　and　a　25%　reduction　in　retention　time　when　scaling　to　32×32　arrays.　Through　cell　layout　optimization,　we　achieved　a　two-fold　enhancement　in　computational　current　along　with　a　5.5　dB　improvement　in　signal-to-noise　ratio　(SNR).　©　2025　IEEE.