A　process-voltage-temperature　(PVT)-robust,　low　power,　low　noise,　and　high　sensitivity,　super-regenerative　(SR)　receiver　is　proposed　in　this　paper.　To　enable　high　sensitivity　and　robust-PVT　operation,　a　fast　locking　phase-locked-loop　(PLL)　with　initial　random　phase　error　reduction　is　proposed　to　continuously　adjust　the　center　frequency　deviations　of　the　SR　oscillator　(SRO)　without　interrupting　the　input　data　stream.　Additionally,　a　concurrent　quenching　waveform　(CQW)　technique　is　devised　to　improve　the　SRO　sensitivity　and　its　noise　performance.　The　proposed　SRO　architecture　is　controlled　by　two　separate　biasing　branches　to　extend　the　sensitivity　accumulation　(SA)　phase　and　reduce　its　noise　during　the　SR　phase,　compared　to　the　conventional　optimal　quenching　waveform　(OQW).　The　proposed　SR　receiver　is　implemented　at　2.46　GHz　center　frequency　in　180　nm　SMIC　CMOS　technology　and　achieves　better　sensitivity,　power　consumption,　noise　performance,　and　PVT　immunity　compared　with　existent　SR　receiver　architectures.