An　ultra-low-power　Frequency　Shift　Keying　(FSK)　demodulator　with　frequency-offset　tolerance　is　designed　in　0.18　mu　m　Complementary　Metal　Oxide　Semiconductor　(CMOS)　process.　The　demodulator　employs　a　period-to-voltage　converter　to　convert　the　periods　of　the　input　FSK-modulated　signal　into　voltage　levels　continuously　while　consuming　ultra-low　power.　Moreover,　a　discrete-time　differentiator　is　adopted　to　utilize　those　converted　voltages　to　recover　the　transmitted　data　while　preventing　the　carrier-frequency　offset　from　deteriorating　the　demodulation　performance.　As　the　experimental　results　indicate,　the　novel　demodulator　can　tolerate　carrier　frequency　variations　up　to　+/-　200　kHz　in　the　case　of　1　Mbps　data　rate　with　a　modulation　index　of　0.32.　It　needs　a　signal-to-noise　ratio　of　16.8　dB　to　achieve　0.1%　bit　error　rate　and　consumes　a　current　of　only　about　49.7　mu　A　from　a　1.8　V　supply.　(c)　2018　Institute　of　Electrical　Engineers　of　Japan.　Published　by　John　Wiley　&　Sons,　Inc.