We　present　a　simple　ripple-transferring　replica　pseudo　phase-locked　loop　(PLL)　technique　for　a　highly　digital　ADC.　The　ADC　is　mainly　constituted　by　main　and　replica　pseudo　PLLs.　Compared　with　conventional　techniques,　this　technique　minimizes　the　main　loop＇s　input　ripple　by　means　of　inverting　the　replica　loop＇s　input　ripple　and　transferring　it　to　the　input　of　the　main　loop　for　the　sum　of　the　two　ripples,　so　the　accuracy　of　the　ADC　should　be　improved.　To　achieve　the　transfer　function　above,　on　the　transferring　path,　a　wide-band　current　mode　amplifier　is　proposed.　The　proposed　ADC　is　well　suited　for　accuracy　and　power　improved　design.　Fabricated　with　a　0.18-mu　m　CMOS　process,　the　ADC　achieves　65-dB　SNDR　while　operating　from　a　1.2-V　supply　and　using　a　1-kHz　input　sine　wave.　Moreover,　the　power　dissipation　is　only　11　mu　W.