Placement　is　the　process　of　determining　the　exact　locations　of　circuit　elements　within　a　chip.　It　is　a　crucial　step　in　very　large　scale　integration　(VLSI)　physical　design,　because　it　affects　routability,　performance,　and　power　consumption　of　a　design.　In　this　paper,　we　develop　a　new　analytical　placer　to　solve　the　VLSI　standard　cell　placement　problem.　The　placer　consists　of　two　phases,　multilevel　global　placement　(GP)　and　detailed　cell　placement　(DP).　In　the　stage　of　GP,　during　the　clustering　stage,　we　use　a　nonlinear　programming　technique　and　a　best-choice　clustering　algorithm　to　take　a　global　view　of　the　whole　netlist　and　placement　information,　and　then　use　an　iterative　local　refinement　technique　during　the　declustering　stage　to　further　distribute　the　cells　and　reduce　the　wirelength.　In　the　stage　of　DP,　we　develop　a　fast　legalization　algorithm　to　make　the　solution　by　global　placement　legal　and　use　a　cell　order　polishing　to　improve　the　legal　solution.　The　proposed　algorithm　is　tested　on　the　IBM　standard　cell　benchmark　circuits　and　Peko　suites.　Experimental　results　show　that　our　placer　obtains　high-quality　results　in　a　reasonable　running　time.