Ignoring　some　cell　overlaps,　global　placement　computes　the　best　position　for　each　cell　to　minimize　the　wirelength.　It　is　a　crucial　step　in　very　large　scale　integration　(VLSI)　physical　design,　because　it　affects　routability,　performance,　and　power　consumption　of　a　design.　With　the　placement　model,　we　develop　a　nonlinear　placement　solver　to　solve　the　VLSI　global　placement　problem.　The　proposed　method　is　tested　on　the　IBM　standard　cell　bench-mark　circuits.　Experimental　results　show　that　it　obtains　high-quality　results　in　a　reasonable　running　time.　©　2012　by　IJAMAS,　CESER　Publications.