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author:

Chen, Jianli (Chen, Jianli.) [1] | Zhu, Ziran (Zhu, Ziran.) [2] | Guo, Longkun (Guo, Longkun.) [3] (Scholars:郭龙坤) | Tseng, Yu-Wei (Tseng, Yu-Wei.) [4] | Chang, Yao-Wen (Chang, Yao-Wen.) [5]

Indexed by:

EI SCIE

Abstract:

Along with device scaling, the drain-to-drain abutment (DDA) and fence region constraints arise as emerging challenges in modern circuit designs, incurring additional difficulties, especially for designs with mixed-cell-height standard cells which have prevailed in advanced technology. This article presents the first work to address the mixed-cell-height placement problem considering the DDA and fence region constraints from post-global placement throughout the detailed placement. Our algorithm consists of three major stages: 1) preprocessing; 2) legalization; and 3) detailed placement. At the preprocessing stage, we align cells to the desired rows that meet the region constraint, considering the total cell displacement and the distribution ratio of source nodes to drain nodes simultaneously. After deciding the cell ordering of every row, we first propose an interval concept to handle fixed macros and fence regions and then apply the robust modulus-based matrix splitting iteration method to remove all cell overlaps with minimized total displacement at the legalization stage. For detailed placement, unlike the existing works that can handle the DDA constraint only for single rows, we propose a satisfiability-based approach that considers the whole layout to fix the DDA violations more effectively. Besides, we further present an integer linear program (ILP)-based method to optimize the cell displacement without increasing the DDA violations. Compared with a shortest-path method, experimental results show that our proposed algorithm can significantly reduce cell violations, average cell displacement, and maximum cell displacement, in a comparable runtime.

Keyword:

Degradation Detailed placement drain-to-drain abutment (DDA) FinFETs legalization modulus-based matrix splitting iteration method physical design Rails satisfiability (SAT) Standards Stress Transistors Transmission line matrix methods

Community:

  • [ 1 ] [Chen, Jianli]Fudan Univ, State Key Lab ASIC & Syst, Shanghai 200433, Peoples R China
  • [ 2 ] [Zhu, Ziran]Southeast Univ, Natl ASIC Syst Engn Ctr, Sch Elect Sci & Engn, Nanjing 210096, Peoples R China
  • [ 3 ] [Guo, Longkun]Fuzhou Univ, Coll Math & Comp Sci, Fuzhou 350116, Peoples R China
  • [ 4 ] [Tseng, Yu-Wei]Natl Taiwan Univ, Grad Inst Elect Engn, Taipei 106, Taiwan
  • [ 5 ] [Chang, Yao-Wen]Natl Taiwan Univ, Grad Inst Elect Engn, Taipei 106, Taiwan
  • [ 6 ] [Chang, Yao-Wen]Natl Taiwan Univ, Dept Elect Engn, Taipei 106, Taiwan
  • [ 7 ] [Chang, Yao-Wen]Acad Sinica, Res Ctr Informat Technol Innovat, Taipei 115, Taiwan

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Source :

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS

ISSN: 0278-0070

Year: 2022

Issue: 4

Volume: 41

Page: 1103-1115

2 . 9

JCR@2022

2 . 7 0 0

JCR@2023

ESI Discipline: ENGINEERING;

ESI HC Threshold:66

JCR Journal Grade:2

CAS Journal Grade:3

Cited Count:

WoS CC Cited Count: 2

SCOPUS Cited Count: 4

ESI Highly Cited Papers on the List: 0 Unfold All

WanFang Cited Count:

Chinese Cited Count:

30 Days PV: 2

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