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author:

Chen, Jianli (Chen, Jianli.) [1] | Lin, Zhifeng (Lin, Zhifeng.) [2] | Xie, Yanyue (Xie, Yanyue.) [3] | Zhu, Wenxing (Zhu, Wenxing.) [4] (Scholars:朱文兴) | Chang, Yao-Wen (Chang, Yao-Wen.) [5]

Indexed by:

SCIE

Abstract:

Mixed-cell-height standard cells are prevailingly used in advanced technologies to achieve better design tradeoffs among timing, power, and routability. As feature size decreases, the placement of cells with multiple threshold voltages may violate the complex minimum-implant-area (MIA) layer rule arising from the limitations of patterning technologies. Existing works consider the mixed-cell-height placement problem only during legalization or handle the MIA constraints during detailed placement. In this article, we address the mixed-cell-height placement problem with MIA constraints in two major stages: 1) post-global placement (Post-GP) and 2) MIA-aware legalization. In the Post-GP stage, we first present a continuous and differentiable cost function to address the Vdd/Vss alignment constraints and add weighted pseudonets to MIA-violation cells dynamically. Then, we propose a proximal optimization method based on the given global placement result to simultaneously consider Vdd/Vss alignment constraints, MIA constraints, cell distribution, cell displacement, and total wirelength. In the MIA-aware legalization stage, we develop a graph-based method to cluster cells of specific threshold voltages and apply a strip-packing-based binary linear programming to reshape cells. Then, we propose a matching-based technique to resolve intrarow MIA violations and reduce filler insertion. Furthermore, we formulate inter-row MIA-aware legalization as a quadratic programming problem, which is efficiently solved by a modulus-based matrix splitting iteration method. Finally, MIA-aware cell allocation and refinement are performed to further improve the result. Experimental results show that without any extra area overhead, our algorithm still can achieve 5.4% shorter final total wirelength than the state-of-the-art work.

Keyword:

Circuit synthesis Law Minimum-implant-area (MIA) mixed-cell-height placement modulus-based matrix splitting iteration method Periodic structures physical design Pins Standards Threshold voltage Timing

Community:

  • [ 1 ] [Chen, Jianli]Fudan Univ, State Key Lab ASIC & Syst, Shanghai 200433, Peoples R China
  • [ 2 ] [Chen, Jianli]Fuzhou Univ, Ctr Discrete Math & Theoret Comp Sci, Fuzhou 350116, Peoples R China
  • [ 3 ] [Zhu, Wenxing]Fuzhou Univ, Ctr Discrete Math & Theoret Comp Sci, Fuzhou 350116, Peoples R China
  • [ 4 ] [Lin, Zhifeng]Fuzhou Univ, Coll Math & Comp Sci, Fuzhou 350116, Peoples R China
  • [ 5 ] [Xie, Yanyue]Northeastern Univ, Dept Elect & Comp Engn, Boston, MA 02115 USA
  • [ 6 ] [Zhu, Wenxing]Peng Cheng Lab, Dept Math & Theory, Shenzhen 518055, Peoples R China
  • [ 7 ] [Chang, Yao-Wen]Natl Taiwan Univ, Dept Elect Engn, Grad Inst Elect Engn, Taipei 106, Taiwan
  • [ 8 ] [Chang, Yao-Wen]Natl Taiwan Univ, Dept Comp Sci & Informat Engn, Taipei 106, Taiwan

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Source :

IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS

ISSN: 0278-0070

Year: 2022

Issue: 11

Volume: 41

Page: 4639-4652

2 . 9

JCR@2022

2 . 7 0 0

JCR@2023

ESI Discipline: ENGINEERING;

ESI HC Threshold:66

JCR Journal Grade:2

CAS Journal Grade:3

Cited Count:

WoS CC Cited Count: 3

SCOPUS Cited Count:

ESI Highly Cited Papers on the List: 0 Unfold All

WanFang Cited Count:

Chinese Cited Count:

30 Days PV: 6

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